Source Code Separation and Generation for Heterogeneous Central Processing Unit (CPU) Computational Devices
Abstract
An example method includes obtaining annotated source code and based at least in part on a first annotation, separating the source code into first and second source code portions. The method also includes generating from the first source code portion a first source code stream to be supplied for compilation by a first compiler, the first source code stream augmented, based on the first annotation, to include additional coordination code not present in the obtained source code, and the first compiler specific to the first-type subset of the target CPUs. The method further includes generating from the second source code portion a second source code stream to be supplied for compilation by a second compiler, the second compiler specific to a second-type subset of the target CPUs. The target CPUs of the first- and second-type subsets have one or more different functionalities.
Claims
exact text as granted — not AI-modifiedWe claim:
1 . A method of preparing source code for compilation for, and eventual coordinated execution on, a heterogeneous plurality of target CPUs, the method comprising:
obtaining source code annotated to identify at least a first portion thereof suitable for execution on a first-type subset of the target CPUs; based at least in part on a first annotation, separating the source code into first and second source code portions; generating from the first source code portion a first source code stream to be supplied for compilation by a first compiler, the first source code stream augmented, based on the first annotation, to include additional coordination code not present in the obtained source code, and the first compiler specific to the first-type subset of the target CPUs; and generating from the second source code portion a second source code stream to be supplied for compilation by a second compiler, the second compiler specific to a second-type subset of the target CPUs, wherein the target CPUs of the first- and second-type subsets have one or more different functionalities.Join the waitlist — get patent alerts
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