Architectures for an Implantable Medical Device System

Abstract

An improved architecture for an implantable medical device such as an implantable pulse generator (IPG) is disclosed. In one embodiment, the various functional blocks for the IPG are incorporated into a signal integrated circuit (IC). Each of the functional blocks communicates with each other, and with other off-chip devices if necessary, via a centralized bus governed by a communication protocol. To communicate with the bus and to adhere to the protocol, each circuit block includes bus interface circuitry adherent with that protocol. Because each block complies with the protocol, any given block can easily be modified or upgraded without affecting the design of the other blocks, facilitating debugging and upgrading of the IPG circuitry. Moreover, because the centralized bus can be taken off the integrated circuit, extra circuitry can easily be added off chip to modify or add functionality to the IPG.

What is claimed is: 
     
         1 . An implantable stimulator device comprising a plurality of electrodes, comprising:
 a first integrated circuit comprising a first stimulation circuitry block for controlling stimulation of a plurality of N first electrodes;   a second integrated circuit similarly constructed to the first integrated circuit, wherein the second integrated circuit comprises a second stimulation circuitry block for controlling stimulation of a plurality of N second electrodes to thereby double the electrode capacity of the implantable stimulator device to 2N electrodes; and   a bus comprising a plurality of signals, wherein the bus signals are connected to the first and second integrated circuits.   
     
     
         2 . The device of  claim 1 , wherein the first and second stimulation circuitry blocks respectively comprise first and second digital-to-analog converter circuitry for respectively providing stimulation to the plurality of first and second electrodes. 
     
     
         3 . The device of  claim 1 , further comprising an electrode array with 2N electrodes configured to provide stimulation to a patient's tissue, wherein the 2N electrodes of the electrode array are each coupled to one of the first and second electrodes. 
     
     
         4 . The device of  claim 3 , wherein the electrode array comprises a plurality of electrode leads. 
     
     
         5 . The device of  claim 3 , wherein the electrode array couples to the first and second electrodes via one or more lead connectors. 
     
     
         6 . The device of  claim 5 , further comprising a case, wherein the first and second integrated circuits and the bus are within the case, and wherein the one or more lead connectors are affixed in a header connector comprising part of the case. 
     
     
         7 . The device of  claim 1 , further comprising a controller, wherein the controller controls the first and second integrated circuits via the bus, wherein the bus signals are connected to the controller. 
     
     
         8 . The device of  claim 7 , wherein the controller comprises an integrated circuit separate from the first and second integrated circuits. 
     
     
         9 . The device of  claim 7 , wherein the controller resides on one of the first or second integrated circuits. 
     
     
         10 . The device of  claim 1 , wherein communication on the bus occurs in accordance with an address-before-data protocol. 
     
     
         11 . The device of  claim 1 , wherein each of the first and second integrated circuits further comprises a plurality of functional blocks each connected to the bus signals. 
     
     
         12 . The device of  claim 11 , wherein the first and second stimulation circuitry blocks and the plurality of functional blocks on the first and second integrated circuits are each connected to the bus using bus interface circuitry. 
     
     
         13 . The device of  claim 1 , wherein the first integrated circuit comprises a master for controlling the second integrated circuit as a slave. 
     
     
         14 . The device of  claim 1 , wherein N is equal to three or more. 
     
     
         15 . The device of  claim 1 , wherein the bus signals comprise (i) a plurality of first signals for carrying both data and addresses associated with the data, and (ii) at least one second signal for controlling reading and writing of the data at their associated addresses. 
     
     
         16 . The device of  claim 15 , wherein the at least one second signal comprises a write enable signal line and a read enable signal line. 
     
     
         17 . The device of  claim 15 , wherein the at least one second signal comprises an address latch enable signal line for latching a read or write address. 
     
     
         18 . The device of  claim 15 , wherein each of the first signals carries both data and addresses associated with the data. 
     
     
         19 . An implantable stimulator device comprising a plurality of electrodes, comprising:
 a first integrated circuit comprising a first stimulation circuitry block for controlling stimulation of a plurality of N first electrodes;   a second integrated circuit similarly constructed to the first integrated circuit, wherein the second integrated circuit comprises a second stimulation circuitry block for controlling stimulation of a plurality of N second electrodes to thereby double the electrode capacity of the implantable stimulator device to 2N electrodes;   a controller for controlling the first and second integrated circuits; and   a bus comprising a plurality of signals, wherein the bus signals are connected to the first and second integrated circuits and to the controller.   
     
     
         20 . The device of  claim 19 , wherein the controller comprises an integrated circuit separate from the first and second integrated circuits. 
     
     
         21 . The device of  claim 19 , further comprising:
 one or more electrode leads with 2N distal electrodes configured to provide stimulation to a patient's tissue, wherein the 2N electrodes of the one or more electrode leads are each coupled to one of the first and second electrodes;   a case, wherein the first and second integrated circuits and the bus are within the case; and   one or more lead connectors within the case and configured to receive proximal ends of the one or more electrode leads.