Programmable filter in an amplifier

Abstract

The disclosure provides an amplifier. The amplifier includes a first transistor that receives a first input and generates a first load current. A first output node is coupled to a power supply through a first load resistor. The first load resistor receives the first load current. A first capacitor network is coupled to the first output node and draws a first capacitive current from the first output node. A first current buffer is coupled between the first output node and the first transistor. A current through the first current buffer is a summation of the first load current and the first capacitive current.

What is claimed is: 
     
         1 . An amplifier comprising:
 a first transistor configured to receive a first input and configured to generate a first load current;   a first output node coupled to a power supply through a first load resistor, the first load resistor configured to receive the first load current;   a first capacitor network coupled to the first output node and configured to draw a first capacitive current from the first output node; and   a first current buffer coupled between the first output node and the first transistor, wherein a current through the first current buffer is a summation of the first load current and the first capacitive current.   
     
     
         2 . The amplifier of  claim 1  further comprising:
 a second transistor configured to receive a second input and configured to generate a second load current; 
 a second output node coupled to a power supply through a second load resistor, the second load resistor configured to receive the second load current; 
 a second capacitor network coupled to the second output node and configured to draw a second capacitive current from the second output node; and 
 a second current buffer coupled between the second output node and the second transistor, wherein a current through the second current buffer is a summation of the second load current and the second capacitive current. 
 
     
     
         3 . The amplifier of  claim 1 , wherein the first current buffer is a BJT cascode transistor whose base terminal is coupled to a first bias voltage, whose collector terminal is coupled to the first output node, and whose emitter terminal is coupled to the first transistor. 
     
     
         4 . The amplifier of  claim 2 , wherein the second current buffer is a BJT cascode transistor whose base terminal is coupled to a second bias voltage, whose collector terminal is coupled to the second output node, and whose emitter terminal is coupled to the second transistor. 
     
     
         5 . The amplifier of  claim 1  further comprising a filter network, wherein the filter network comprises:
 the first capacitor network coupled in parallel to the first current buffer; 
 the second capacitor network coupled in parallel to the second current buffer; and 
 a primary switch coupled between the first capacitor network and the second capacitor network. 
 
     
     
         6 . The amplifier of  claim 5 , wherein the first capacitor network comprises:
 a first capacitor coupled to the first output node; and   a first switch coupled between the first capacitor and the emitter terminal of the first current buffer.   
     
     
         7 . The amplifier of  claim 5 , wherein the second capacitor network comprises:
 a second capacitor coupled to the second output node; and   a second switch coupled between the second capacitor and the emitter terminal of the second current buffer.   
     
     
         8 . The amplifier of  claim 1 , wherein when the primary switch is inactivated:
 the first switch and the second switch are activated;   the first capacitive current flows through the first capacitor and the first switch; and   the second capacitive current flows through the second capacitor and the second switch.   
     
     
         9 . The amplifier of  claim 1  further comprising a first fixed capacitor coupled between the first output node and a ground terminal, and a second fixed capacitor coupled between the second output node and the ground terminal. 
     
     
         10 . The amplifier of  claim 1  further comprising:
 an impedance coupled between the first transistor and the second transistor; 
 a first biasing current source coupled between the first transistor and the ground terminal; and 
 a second biasing current source coupled between the second transistor and the ground terminal. 
 
     
     
         11 . A method comprising:
 inactivating a primary switch;   generating a first load current in response to a first input, the first load current received by a first load resistor;   providing a first capacitive current to a first capacitor network; and   providing a current that is a summation of the first load current and the first capacitive current to a first current buffer, the first current buffer coupled in parallel to the first capacitor network.   
     
     
         12 . The method of  claim 11  further comprising:
 generating a second load current in response to a second input, the second load current received by a second load resistor; 
 providing the second capacitive current to a second capacitor network; and 
 providing a current that is a summation of the second load current and the second capacitive current to a second current buffer, the second current buffer coupled in parallel to the second capacitor network. 
 
     
     
         13 . The method of  claim 11 , wherein providing the first capacitive current to the first capacitor network further comprises activating a first switch in the first capacitor network, and providing the second capacitive current to the second capacitor network further comprises activating a second switch in the second capacitor network, wherein the primary switch is coupled in between the first switch and the second switch. 
     
     
         14 . The method of  claim 11  further comprising generating the first load current by a first transistor in response to the first input, and generating the second load current by a second transistor in response to the second input. 
     
     
         15 . An amplifier comprising:
 a first output node coupled to a power supply through a first load resistor;   a second output node coupled to the power supply through a second load resistor;   a first current buffer coupled to the first output node;   a second current buffer coupled to the second output node;   a filter network coupled between the first output node and the second output node, the filter network comprising:
 a first capacitor network coupled between the first output node and the second current buffer; 
 a second capacitor network coupled between the second output node and the first current buffer; and 
 a primary switch coupled between the first capacitor network and the second capacitor network. 
   
     
     
         16 . The amplifier of  claim 15 , wherein:
 the first current buffer is a BJT cascode transistor whose base terminal is coupled to a bias voltage, whose collector terminal is coupled to the first output node, and whose emitter terminal is coupled to a first transistor; and   the second current buffer is a BJT cascode transistor whose base terminal is coupled to a bias voltage, whose collector terminal is coupled to the second output node, and whose emitter terminal is coupled to a second transistor.   
     
     
         17 . The amplifier of  claim 15 , wherein the first capacitor network comprises:
 a first capacitor coupled to the first output node; and   a first switch coupled between the emitter terminal of the second current buffer and the first capacitor.   
     
     
         18 . The amplifier of  claim 15 , wherein the second capacitor network comprises:
 a second capacitor coupled to the second output node; and   a second switch coupled between the emitter terminal of the first current buffer and the second capacitor.   
     
     
         19 . A receiver comprising:
 a receive antenna configured to receive a signal and configured to generate a first input and a second input; and   an amplifier coupled to the receive antenna, the amplifier comprising:
 a first transistor configured to receive the first input and configured to generate a first load current; 
 a first output node coupled to a power supply through a first load resistor, the first load resistor configured to receive the first load current; 
 a first capacitor network coupled to the first output node and configured to draw a first capacitive current from the first output node; and 
 a first current buffer coupled between the first output node and the first transistor, wherein a current through the first current buffer is a summation of the first load current and the first capacitive current; 
   an IF filter coupled to the amplifier and configured to generate a filtered non-zero IF signal from a signal received from the amplifier;   an ADC (analog to digital converter) coupled to the IF filter and configured to sample the filtered non-zero IF signal to generate a valid data; and   a processor coupled to the ADC and configured to process the valid data.   
     
     
         20 . The receiver of  claim 19 , wherein the amplifier further comprises:
 a second transistor configured to receive the second input and configured to generate a second load current;   a second output node coupled to a power supply through a second load resistor, the second load resistor configured to receive the second load current;   a second capacitor network coupled to the second output node and configured to draw a second capacitive current from the second output node; and   a second current buffer coupled between the second output node and the second transistor, wherein a current through the second current buffer is a summation of the second load current and the second capacitive current.