Semiconductor device

Abstract

To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×10 16 /cm 3 , and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.

1 - 9 . (canceled) 
     
     
         10 . A semiconductor device comprising:
 a substrate;   a compound semiconductor layer that is formed over the substrate and that includes a group III nitride compound;   a p-type well that is formed in the compound semiconductor layer;   a source region that is formed in the compound semiconductor layer and that is an n-type impurity layer;   a low-concentration n-type region that is formed in the compound semiconductor layer and that is linked to the p-type well;   a drain region that is formed in the compound semiconductor layer, that is located on a side opposite to the p-type well via the low-concentration n-type region, and that is an n-type impurity layer;   a gate insulating film that is formed over a portion of the p-type well located between the source region and the low-concentration n-type region; and   a gate electrode that is formed over the gate insulating film,   wherein a p-type impurity concentration of the compound semiconductor layer is lower than that of the p-type well,   wherein an n-type impurity concentration of the compound semiconductor layer is less than an n-type impurity concentration of the low-concentration n-type region, and   wherein the n-type impurity concentration of the low-concentration n-type region is less than an n-type impurity concentration of the drain region.   
     
     
         11 . The semiconductor device according to  claim 10 ,
 wherein a concentration of p-type impurities in the compound semiconductor layer and a concentration of n-type impurities in the compound semiconductor layer are each less than 1×10 16 /cm 3 .   
     
     
         12 . The semiconductor device according to  claim 10 ,
 wherein the source region is formed within the p-type well.   
     
     
         13 . The semiconductor device according to  claim 10 , comprising a high-resistance compound semiconductor layer that is located between the substrate and the compound semiconductor layer and that has a sheet resistance higher than that of the compound semiconductor layer. 
     
     
         14 . The semiconductor device according to  claim 13 , comprising a buffer layer located between the high-resistance compound semiconductor layer and the substrate. 
     
     
         15 . The semiconductor device according to  claim 10 ,
 wherein the p-type impurity concentration of the p-type well is in a range from 1×10 16  cm −3  to 1×10 19  cm −3 , inclusive.   
     
     
         16 . The semiconductor device according to  claim 10 , comprising:
 an insulating layer formed over the low-concentration n-type region; and   a field plate electrode formed over the insulating layer.   
     
     
         17 . The semiconductor device according to  claim 10 ,
 wherein the compound semiconductor layer is a nitride gallium layer.   
     
     
         18 . The semiconductor device according to  claim 10 ,
 wherein the n-type impurity concentration of the low-concentration n-type region is in a range from 1×10 16  cm −3  to 1×10 19  cm −3 , inclusive, and   wherein the n-type impurity concentration of the drain region is in a range from 1×10 19  cm −3  to 1×10 22  cm −3 , inclusive.