Stacked semiconductor package

Abstract

A stacked semiconductor package including a first printed circuit board and a second printed circuit board is provided. The first printed circuit board may include a first surface upon which a first semiconductor chip is mounted and a second surface upon which at least one connecting structure is attached. The first printed circuit board may further include at least one thermal via and a heat sink and the at least one thermal via and the heat sink may be disposed under the first semiconductor chip with the heat sink being disposed between the first surface and the second surface. The second printed circuit board may include a third surface upon which a second semiconductor chip is mounted. The second printed circuit board may be disposed under the first printed circuit board with the at least one connecting structure connecting the first printed circuit board to the second printed circuit board.

1 . (canceled) 
     
     
         2 . A stacked semiconductor package comprising:
 a first printed circuit board including a first surface upon which a first semiconductor chip is mounted and a second surface upon which at least one connecting structure is attached, the first printed circuit board further including a heat sink, the heat sink being disposed under the first semiconductor chip, wherein the first semiconductor chip and the first printed circuit board are electrically connected; and   a second printed circuit board including a third surface upon which a second semiconductor chip is mounted, the second printed circuit board being disposed under the first printed circuit board, the at least one connecting structure connecting the first printed circuit board to the second printed circuit board,   wherein the second surface of the first printed circuit board has a recess.   
     
     
         3 . The stacked semiconductor package of  claim 2 , wherein the heat sink includes a material having a substantially same coefficient of thermal expansion as the first semiconductor chip. 
     
     
         4 . The stacked semiconductor package of  claim 3 , wherein the heat sink includes one of copper, copper alloy, and aluminum. 
     
     
         5 . The stacked semiconductor package of  claim 2 , wherein the heat sink is arranged within the first printed circuit board at a position corresponding to the first semiconductor chip, and has an area corresponding to the first semiconductor chip. 
     
     
         6 . The stacked semiconductor package of  claim 2 , further comprising:
 a molding material covering at least one portion of the second semiconductor chip and defining at least one molding via hole exposing an upper surface of the second semiconductor chip.   
     
     
         7 . The stacked semiconductor package of  claim 2 , wherein the first semiconductor chip includes a memory device, and the second semiconductor chip includes a logic device. 
     
     
         8 . The stacked semiconductor package of  claim 2 , further comprising:
 at least one other connecting structure electrically connecting the second semiconductor chip to the second printed circuit board.   
     
     
         9 . The stacked semiconductor package of  claim 2 , wherein the heat sink is disposed between the first surface and the second surface. 
     
     
         10 . The stacked semiconductor package of  claim 2 , wherein the first semiconductor chip and the first printed circuit board are connected by at least one bonding wire. 
     
     
         11 . The stacked semiconductor package of  claim 2 , wherein the second semiconductor chip is mounted on the second circuit board by a flip chip type. 
     
     
         12 . The stacked semiconductor package of  claim 2 , further comprising a heat diffusion material between the heat sink of the first printed circuit board and the second semiconductor chip of the second printed circuit board. 
     
     
         13 . The stacked semiconductor package of  claim 12 , wherein:
 the first printed circuit board further comprises at least one thermal via under the first semiconductor chip; and   the thermal via extends into the recess to contact the heat diffusion material.   
     
     
         14 . The stacked semiconductor package of  claim 12 , wherein the heat diffusion material comprises an electrically insulating material. 
     
     
         15 . The stacked semiconductor device of  claim 14 , wherein the heat diffusion material is separated from the first printed circuit board by the recess in the second surface of the first printed circuit board. 
     
     
         16 . The stacked semiconductor device of  claim 14 , wherein the heat diffusion material faces the recess.