Traceable integrated circuits and production method thereof

Abstract

An embodiment of a method for producing traceable integrated circuits includes forming on a wafer of semiconductor material functional regions for implementing specific functionalities of corresponding integrated circuits, forming at least one seal ring around each functional region of the corresponding integrated circuit, and forming on each integrated circuit at least one marker indicative of information of the integrated circuit. Forming on each integrated circuit at least one marker may include forming the at least one marker on at least a portion of the respective seal ring that is visible.

1 . A method, comprising:
 forming on a wafer of semiconductor material including a plurality of die locations a functional region at each die location for implementing specific functionalities of a corresponding integrated circuit;   forming a seal ring around the functional region of each integrated circuit, and   forming on a top surface of each seal ring at least one marker that provides die information.   
     
     
         2 . The method of  claim 1 , wherein the die information identifies a position of the die location within the wafer. 
     
     
         3 . The method of  claim 1 ,
 wherein forming the seal ring comprises forming a stack of interconnected layers, said stack including a top layer having a thickness; and   wherein forming at least one marker comprises forming a groove in a top surface of said top layer, said groove positioned in between and away from an inner and outer perimeter edge of the seal ring and having a depth that is less than said thickness.   
     
     
         4 . The method of  claim 3 , further comprising depositing a passivation layer on the top surface of the seal ring and within said groove. 
     
     
         5 . The method of  claim 1 ,
 wherein forming the seal ring comprises:
 forming a stack of interconnected layers, said stack including a top layer made of a first metal material having a first visible color; and 
 forming a cover layer of a second metal material having a second visible color different from the first visible color and having a thickness; and 
   wherein forming at least one marker comprises forming a groove in the cover layer, said groove positioned in between and away from an inner and outer perimeter edge of the seal ring and having a depth that is at least said thickness.   
     
     
         6 . The method of  claim 5 , further comprising depositing a passivation layer on the cover layer and within said groove. 
     
     
         7 . The method of  claim 5 , wherein the first metal material is copper and the second metal material is aluminum. 
     
     
         8 . The method of  claim 1 , wherein forming the at least one marker includes forming a plurality of grooves on the top surface of the seal ring, each groove being associable with one between a first value and a second value of a binary number system, and wherein locations without grooves are associated with the other between the second value and the first value. 
     
     
         9 . The method of  claim 1 , further comprising performing a chemical-mechanical polishing of the top surface of the seal ring. 
     
     
         10 . The method of  claim 1 , further comprising depositing a passivation layer on the seal ring, said passivation layer protecting said at least one marker. 
     
     
         11 . The method of  claim 1 , wherein forming the seal ring comprises:
 forming a plurality of conductive layers in a stack; and   forming spacers between adjacent conductive layers.   
     
     
         12 . The method of  claim 11 , wherein a top surface of a last conductive layer of said plurality of conductive layers receives the at least one marker. 
     
     
         13 . The method of  claim 11 , further comprising forming at least one extension protruding from at least one of said plurality of conductive layers, and wherein forming the at least one marker comprises forming said at least one marker on said extension. 
     
     
         14 . The method of  claim 11 , wherein a last one of said plurality of conductive layers is made of a first conductive material, further comprising:
 depositing on said last one of the conductive layers a coating layer made of a second conductive material different from the first conductive material; and   wherein forming the at least one marker comprises forming said at least one marker on said coating layer.   
     
     
         15 . The method of  claim 14 , wherein forming said at least one marker on said coating layer comprises forming at least one probe mark on the coating layer. 
     
     
         16 . The method of  claim 14 , wherein the first conductive material includes copper and the second conductive material includes aluminum. 
     
     
         17 . The method of  claim 1 , wherein forming the at least one marker comprises forming a grooves by means of a laser technique. 
     
     
         18 . A method, comprising:
 forming on a wafer of semiconductor material including a plurality of die locations a functional region at each die location for implementing specific functionalities of a corresponding integrated circuit;   forming a seal ring around the functional region of each integrated circuit, said seal ring including a stack of interconnected layers, said stack including a top layer having a thickness; and   forming a groove in a top surface of said top layer, said groove positioned in between and away from an inner and outer perimeter edge of the seal ring and having a depth that is less than said thickness, said groove providing die information.   
     
     
         19 . The method of  claim 18 , wherein said die information identifies a position of the die location within the wafer. 
     
     
         20 . A method, comprising:
 forming on a wafer of semiconductor material including a plurality of die locations a functional region at each die location for implementing specific functionalities of a corresponding integrated circuit;   forming a seal ring around the functional region of each integrated circuit, said seal ring including a stack of interconnected layers including a top layer made of a first metal material having a first visible color;   forming a cover layer on the top layer, said cover layer made of a second metal material having a second visible color different from the first visible color and having a thickness; and   forming a groove in the cover layer, said groove positioned in between and away from an inner and outer perimeter edge of the seal ring and having a depth that is at least said thickness, said groove providing die information.   
     
     
         21 . The method of  claim 20 , wherein said die information identifies a position of the die location within the wafer.