Memory Device

Abstract

A memory device includes a memory cell array including a plurality of memory cells, a common source line to which sources of the plurality of memory cells are commonly connected, and a second electrical connection path further connecting the common source line to a ground voltage using erase-mode memory cells when the common source line forms a first electrical connection path and is connected to the ground voltage.

1 - 18 . (canceled) 
     
     
         19 . A memory device, comprising:
 a sense amplifier;   a data memory cell in which data are stored and erased;   an erase mode memory cell in which data are only erased;   a common source line, connected to the data memory cell and the erase mode memory cell, to provide a first electrical connection path from the data memory cell to a ground voltage;   a word line connected to the data memory cell and the erase mode memory cell;   a first bit line that connects the sense amplifier to the data memory cell; and   a second bit line that connects the erase mode memory cell to the ground voltage,   wherein, when a voltage is applied to the word line, the erase mode memory cell changes to an on-state to provide a second electrical connection path from the data memory cell to the ground voltage.   
     
     
         20 . The memory device according to  claim 19 , further comprising a bit line grounding switch that connects the second bit line to the ground voltage when data are read from the data memory cell. 
     
     
         21 . The memory device according to  claim 20 , wherein the bit line grounding switch disconnects the second bit line from the ground voltage when data are written to the data memory cell. 
     
     
         22 . The memory device according to  claim 20 , wherein the bit line grounding switch disconnects the second bit line from the ground voltage when data are erased from the data memory cell. 
     
     
         23 . The memory device according to  claim 19 , further comprising a bit line selector that connects the first bit line to the sense amplifier. 
     
     
         24 . The memory device according to  claim 23 , further comprising a y-address decoder that decodes a y-address signal and controls the bit line selector based on the decoded y-address signal. 
     
     
         25 . The memory device according to  claim 19 , further comprising an x-address decoder that decodes an x-address signal and applies the voltage to the word line based on the decoded x-address signal. 
     
     
         26 . The memory device according to  claim 19 , further comprising a source line driver that connects the common source line to the ground voltage via a source line. 
     
     
         27 . The memory device according to  claim 26 , wherein the common source line is a diffusion layer line having a resistance, and the source line is a metal line having a resistance lower than the resistance of the common source line. 
     
     
         28 . A memory device, comprising:
 a sense amplifier;   a bit line selector connected to the sense amplifier;   a plurality of data memory cells in which data are stored and erased;   a plurality of erase mode memory cells in which data are only erased;   a common source line, connected to the data memory cells and the erase mode memory cells, to provide a first electrical connection path from the data memory cells to a ground voltage;   a plurality of word lines connected to the data memory cells and the erase mode memory cells, each word line being connected to one of the erase mode memory cells;   a plurality of bit lines connected to the bit line selector and the data memory cells; and   a ground bit line that connects the erase mode memory cells to the ground voltage,   wherein, when a voltage is applied to one of the word lines, the erase mode memory cell connected to the word line changes to an on-state to provide a second electrical connection path from the data memory cells connected to the word line to the ground voltage,   wherein a y-address decoder decodes a y-address signal and controls the bit line selector based on the decoded y-address signal, and   wherein an x-address decoder decodes an x-address signal and applies a voltage to one of the plurality of word lines based on the decoded x-address signal.   
     
     
         29 . The memory device according to  claim 28 , further comprising a bit line grounding switch that connects the ground bit line to the ground voltage when data are read from one of the plurality of data memory cells. 
     
     
         30 . The memory device according to  claim 29 , wherein the bit line grounding switch disconnects the ground bit line from the ground voltage when data are written to one of the plurality of data memory cells. 
     
     
         31 . The memory device according to  claim 29 , wherein the bit line grounding switch disconnects the ground bit line from the ground voltage when data are erased from one of the plurality of data memory cells. 
     
     
         32 . The memory device according to  claim 19 , further comprising a source line driver that connects the common source line to the ground voltage via a source line.