Semiconductor memory device

Abstract

A semiconductor device including a plurality of first diffusion layers that are formed over a semiconductor layer and disposed at predetermined intervals in a first direction, a plurality of second diffusion layers that are formed over the semiconductor layer, isolated from the first diffusion layers in a second direction orthogonal to the first direction, and disposed at the predetermined intervals in the first direction, a plurality of first regions that have a predetermined width in the first direction for separating the first diffusion layers from each other, a plurality of second regions that align with the first regions in the second direction and have the predetermined width for separating the second diffusion layers from each other, and a plurality of contacts that are formed over the first diffusion layers and over the second diffusion layers.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a plurality of first diffusion layers that are formed over a semiconductor layer and disposed at predetermined intervals in a first direction,   a plurality of second diffusion layers that are formed over the semiconductor layer, isolated from the first diffusion layers in a second direction orthogonal to the first direction, and disposed at the predetermined intervals in the first direction,   a plurality of first regions that have a predetermined width in the first direction for separating the first diffusion layers from each other,   a plurality of second regions that align with the first regions in the second direction and have the predetermined width for separating the second diffusion layers from each other, and   a plurality of contacts that are formed over the first diffusion layers and over the second diffusion layers.   
     
     
         2 . The semiconductor device according to  claim 1 , further comprising:
 a plurality of gates that are long in the second direction, formed over the semiconductor layer exposed by the first regions.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein the plurality of gates are formed over one or both of portions of the semiconductor layer that are exposed by the second regions and have a same pitch. 
     
     
         4 . The semiconductor device of  claim 2 , further comprising a sense amplifier section, wherein the sense amplifier section detects information stored in a memory cell through a bit line, and
 wherein the sense amplifier section includes the plurality of first diffusion layers, the plurality of second diffusion layers, the plurality of first regions, the plurality of second regions, the plurality of contacts, and the plurality of gates.   
     
     
         5 . The semiconductor device according to  claim 2 , wherein the gates are shaped like a strip that is long in the second direction. 
     
     
         6 . The semiconductor device according to  claim 1 ,
 wherein the first diffusion layers are formed by a first conductivity type semiconductor; and   wherein the second diffusion layers are formed by a second conductivity type semiconductor, the second conductivity type semiconductor being different from the first conductivity type semiconductor.   
     
     
         7 . The semiconductor device according to  claim 2 ,
 wherein two of the first diffusion layers serve as a drain and a source so that the two of the first diffusion layers and the gates disposed over the semiconductor layer exposed by the first regions form a transistor; and   wherein two of the second diffusion layers serve as a drain and a source so that the two of the second diffusion layers and the gates disposed over the semiconductor layer exposed by the second regions form a transistor.   
     
     
         8 . The semiconductor device according to  claim 4 , wherein the memory cell and the sense amplifier section form a DRAM. 
     
     
         9 . The semiconductor device according to  claim 4 , wherein the sense amplifier section includes a precharge circuit that equalizes the potentials of a pair of a first bit line and a second bit line in accordance with a first control signal, and a Y switch section that couples the first bit line to a first bus line and the second bit line to a second bus line in accordance with a second control signal. 
     
     
         10 . The semiconductor device according to  claim 9 ,
 wherein the precharge circuit includes a first transistor that is coupled at one end to the first bit line and at the other end to a first power supply, a second transistor that is coupled at one end to the second bit line and at the other end to the first power supply, and an equalizer circuit that is coupled at one end to the first bit line and at the other end to the second bit line;   wherein the Y switch section includes a third transistor that is coupled at one end to the first bit line and at the other end to the first bus line, and a fourth transistor that is coupled at one end to the second bit line and at the other end to the second bus line;   wherein the first control signal is applied to control terminals of the first and second transistors and of the equalizer circuit; and   wherein the second control signal is applied to control terminals of the third and fourth transistors.   
     
     
         11 . A sense amplifier section, comprising:
 a plurality of first diffusion layers that are formed over a semiconductor layer and disposed at predetermined intervals in a first direction,
 a plurality of second diffusion layers that are formed over the semiconductor layer, isolated from the first diffusion layers in a second direction orthogonal to the first direction, and disposed at the predetermined intervals in the first direction, 
 a plurality of first regions that have a predetermined width in the first direction for separating the first diffusion layers from each other, 
 a plurality of second regions that align with the first regions in the second direction and have the predetermined width for separating the second diffusion layers from each other, and 
 a plurality of contacts that are formed over the first diffusion layers and over the second diffusion layers. 
   
     
     
         12 . The sense amplifier section according to  claim 11 , further comprising:
 a plurality of gates formed over the semiconductor layer exposed by the first regions and have a same pitch.   
     
     
         13 . The sense amplifier section according to  claim 11 , wherein the plurality of gates are formed over one or both of portions of the semiconductor layer that are exposed by the second regions. 
     
     
         14 . The sense amplifier section of  claim 12 , wherein the sense amplifier section detects information stored in a memory cell through a bit line. 
     
     
         15 . The sense amplifier section according to  claim 12 , wherein the gates are shaped like a strip that is long in the second direction. 
     
     
         16 . The sense amplifier section according to  claim 11 ,
 wherein the first diffusion layers are formed by a first conductivity type semiconductor; and   wherein the second diffusion layers are formed by a second conductivity type semiconductor, the second conductivity type semiconductor being different from the first conductivity type semiconductor.   
     
     
         17 . The sense amplifier section according to  claim 12 ,
 wherein two of the first diffusion layers serve as a drain and a source so that the two of the first diffusion layers and the gates disposed over the semiconductor layer exposed by the first regions form a transistor; and   wherein two of the second diffusion layers serve as a drain and a source so that the two of the second diffusion layers and the gates disposed over the semiconductor layer exposed by the second regions form a transistor.   
     
     
         18 . A Dynamic Random Access Memory (DRAM) including the sense amplifier section according to  claim 11 , and a memory cell,
 wherein the sense amplifier section detects information stored in the memory cell through a bit line.   
     
     
         19 . The DRAM according to  claim 18 , wherein the bit line includes a first bit line,
 wherein the sense amplifier section includes a precharge circuit that equalizes the potentials of a pair of the first bit line and a second bit line in accordance with a first control signal, and a Y switch section that couples the first bit line to a first bus line and the second bit line to a second bus line in accordance with a second control signal,
 wherein the precharge circuit includes a first transistor that is coupled at one end to the first bit line and at the other end to a first power supply, a second transistor that is coupled at one end to the second bit line and at the other end to the first power supply, and an equalizer circuit that is coupled at one end to the first bit line and at the other end to the second bit line; 
 wherein the Y switch section includes a third transistor that is coupled at one end to the first bit line and at the other end to the first bus line, and a fourth transistor that is coupled at one end to the second bit line and at the other end to the second bus line; 
 wherein the first control signal is applied to control terminals of the first and second transistors and of the equalizer circuit; and 
 wherein the second control signal is applied to control terminals of the third and fourth transistors. 
   
     
     
         20 . A method of forming a semiconductor device, comprising:
 forming a plurality of first diffusion layers over a semiconductor layer and being disposed at predetermined intervals in a first direction,   forming a plurality of second diffusion layers over the semiconductor layer, isolated from the first diffusion layers in a second direction orthogonal to the first direction, and being disposed at the predetermined intervals in the first direction,   separating, by a plurality of first regions that have a predetermined width in the first direction, the first diffusion layers from each other,   providing a plurality of second regions that align with the first regions in the second direction and have the predetermined width for separating the second diffusion layers from each other,   forming a plurality of contacts over the first diffusion layers and over the second diffusion layers; and   forming a plurality of gates that are long in the second direction, over the semiconductor layer exposed by the first regions.