Native pmos device with low threshold voltage and high drive current and method of fabricating the same

Abstract

A native p-type metal oxide semiconductor (PMOS) device that exhibits a low threshold voltage and a high drive current over a varying range of short channel lengths and a method for fabricating the same is discussed in the present disclosure. The source and drain regions of the native PMOS device, each include a strained region, a heavily doped raised region, and a lightly doped region. The gate region includes a stacked layer of a gate oxide having a high-k dielectric material, a metal, and a contact metal. The high drive current of the native PMOS device is primarily influenced by the increased carrier mobility due to the strained regions, the lower drain resistance due to the raised regions, and the higher gate capacitance due to the high-k gate oxide of the native PMOS device.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a deep well region, having a first conductivity type, dividing a substrate into a first substrate region having the first conductivity type and a second substrate region having a second conductivity type different from the first conductivity type;   a first region having a raised portion in the first substrate region, a top side of the raised portion being raised above a top side of the first substrate region;   a second region; and   a third region, between the first region and the second region, laterally displaced from the raised portion.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first region further comprises a strained portion positioned in the first substrate region, and
 wherein a sub-portion of the raised portion is positioned in the strained portion.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the first region further comprises a strained portion, positioned in the first substrate region, having the first conductivity type, and
 wherein a sub-portion of the raised portion, positioned in the strained portion, has a third conductivity type greater than the first conductivity type and the second conductivity type.   
     
     
         4 . The semiconductor device of  claim 3 , wherein a vertical dimension of the strained portion is greater than or equal to a vertical dimension of the raised portion. 
     
     
         5 . The semiconductor device of  claim 3 , wherein the first region further comprises a doped portion having a fourth conductivity type different from the first conductivity type, the second conductivity type, and the third conductivity type,
 wherein a sub-portion of the doped portion is positioned in the strained portion, and   wherein a second sub-portion of the doped portion extends out from the strained portion.   
     
     
         6 . The semiconductor device of  claim 3 , wherein the strained portion comprises a silicon germanium material. 
     
     
         7 . The semiconductor device of  claim 5 , wherein the third region is laterally displaced from the raised portion by the doped portion. 
     
     
         8 . The semiconductor device of  claim 1 , further comprising an isolation region, and
 wherein the raised portion is in at least partial contact with the isolation region.   
     
     
         9 . The semiconductor device of  claim 1 , wherein the second region comprises:
 a second raised portion in the first substrate region;   a strained portion positioned in the first substrate region; and   a sub-portion of the second raised portion positioned in the strained portion.   
     
     
         10 . The semiconductor device of  claim 1 , wherein the third region comprises:
 a first layer having a first thickness and a high-k dielectric material selected from the group consisting of hafnium dioxide and zirconium dioxide;   a second layer having a second thickness greater than the first thickness and having a metal selected from the group consisting of tungsten and titanium; and   a third layer having a third thickness greater than the second thickness and having a contact metal selected from the group consisting of aluminum and copper.   
     
     
         11 . The semiconductor device of  claim 1 , wherein the semiconductor device is characterized as having a threshold voltage of approximately zero volts. 
     
     
         12 . A P-type metal oxide semiconductor (PMOS) device, comprising:
 a deep well region, having a first conductivity type, dividing a substrate into a first substrate region having the first conductivity type and a second substrate region having a second conductivity type different from the first conductivity type;   a first region having a raised portion in the first substrate region, a top side of the raised portion being raised above a top side of the first substrate region;   a second region; and   a third region, between the first region and the second region, laterally displaced from the raised portion.   
     
     
         13 . The PMOS device of  claim 12 , wherein the first region further comprises a strained portion, positioned in the first substrate region, having the first conductivity type, and
 wherein a sub-portion of the raised portion, positioned in the strained portion, has a third conductivity greater than the first and second conductivities.   
     
     
         14 . The PMOS device of  claim 13 , wherein the first region further comprises a doped portion having a fourth conductivity type different from the first conductivity type, the second conductivity type, and the third conductivity type,
 wherein a sub-portion of the doped portion is positioned in the strained portion; and   wherein a second sub-portion of the doped portion extends out from the strained portion.   
     
     
         15 . The PMOS device of  claim 13 , wherein the strained portion comprises a silicon germanium material. 
     
     
         16 . The PMOS device of  claim 12 , further comprising an isolation region, and
 wherein the raised portion is in at least partial contact with the isolation region.   
     
     
         17 . The PMOS device of  claim 12 , wherein the third region comprises:
 a first layer having a first thickness and a high-k dielectric material selected from the group consisting of hafnium dioxide and zirconium dioxide;   a second layer having a second thickness greater than the first thickness and having a metal selected from the group consisting of tungsten and titanium; and   a third layer having a third thickness greater than the second thickness and having a contact metal selected from the group consisting of aluminum and copper.   
     
     
         18 . A semiconductor device, comprising:
 a well region, having a first conductivity type, dividing a substrate into a first substrate region having the first conductivity type and a second substrate region having a second conductivity type different from the first conductivity type;   a source region having a raised portion and a strained portion in the first substrate region, a sub-portion of the raised portion, positioned in the strained portion, having a third conductivity type greater than the first conductivity type and the second conductivity type;   a drain region; and   a gate region, between the source region and the drain region, laterally displaced from the raised portion.   
     
     
         19 . The semiconductor device of  claim 18 , wherein the strained portion comprises a compound semiconductor material. 
     
     
         20 . The semiconductor device of  claim 18 , wherein a vertical dimension of the strained portion is greater than or equal to a vertical dimension of the raised portion.