Methods of forming gate structures for finfet devices and the resulting semiconductor products

Abstract

A transistor device includes first and second spaced-apart active regions positioned in a semiconductor substrate, each of the respective first and second spaced-apart active regions having at least one fin. First and second spaced-apart gate structures are positioned above the respective first and second active regions, each of the first and second gate structures having end surfaces. A gate separation structure is positioned between the first and second spaced-apart gate structures, wherein first and second opposing surfaces of the gate separation structure abut an entirety of the respective end surfaces of the first and second spaced-apart gate structures, and wherein an upper surface of the gate separation structure is positioned at a greater height level above the semiconductor substrate than an upper surface of the at least one fin of each of the respective first and second spaced-apart active regions.

What is claimed: 
     
         1 . A transistor device, comprising:
 first and second spaced-apart active regions positioned in a semiconductor substrate, each of said respective first and second spaced-apart active regions comprising at least one fin;   first and second spaced-apart gate structures positioned above said respective first and second active regions, respectively, each of said first and second gate structures comprising end surfaces; and   a gate separation structure positioned between said first and second spaced-apart gate structures, wherein first and second opposing surfaces of said gate separation structure abut an entirety of said respective end surfaces of said first and second spaced-apart gate structures, and wherein an upper surface of said gate separation structure is positioned at a greater height level above said semiconductor substrate than an upper surface of said at least one fin comprising each of said respective first and second spaced-apart active regions.   
     
     
         2 . The transistor device of  claim 1 , wherein said upper surface of said gate separation structure is positioned at a height level above said semiconductor substrate that is approximately even with a height level of an upper surface of an uppermost conductive material of said first and second gate structures. 
     
     
         3 . The transistor device of  claim 1 , further comprising;
 a first sidewall spacer positioned adjacent opposing side surfaces of said gate separation structure; and   an epitaxial semiconductor material positioned on said at least one fin comprising each of said respective first and second spaced-apart active regions, said epitaxial semiconductor material abutting said first sidewall spacer.   
     
     
         4 . The transistor device of  claim 3 , further comprising a second sidewall spacer positioned adjacent sidewall surfaces of each of said first and second spaced-apart gate structures, said epitaxial semiconductor material further abutting said second sidewall spacers. 
     
     
         5 . The transistor device of  claim 1 , further comprising:
 a third active region positioned in said semiconductor substrate and spaced apart from said first active region, said third active region comprising at least one fin; and   a third gate structure positioned above said third active region, said third gate structure being oriented substantially parallel to said first gate structure, wherein said first and third gate structures have side surfaces, and wherein a portion of said gate separation structure is positioned in an area between said side surfaces of said first and third gate structures.   
     
     
         6 . The transistor device of  claim 1 , wherein each of said first and second spaced-apart gate structures comprise a high-k gate insulation layer and one or more metal layers positioned above said high-k gate insulation layer. 
     
     
         7 . A transistor device, comprising:
 first and second spaced-apart active regions positioned in a semiconductor substrate, each of said respective first and second spaced-apart active regions comprising at least one fin;   first and second spaced-apart gate structures positioned above and extending across said at least one fin of each of said respective first and second spaced-apart active regions, each of said first and second spaced-apart gate structures comprising side surfaces, wherein said first gate structure is oriented parallel to said second gate structure; and   a gate separation structure positioned between adjacent side surfaces of said first and second spaced-apart gate structures, wherein an upper surface of said gate separation structure is positioned at a greater height level above said semiconductor substrate than an upper surface of said at least one fin comprising each of said respective first and second spaced-apart active regions.   
     
     
         8 . The transistor device of  claim 7 , wherein said upper surface of said gate separation structure is positioned at a height level above said semiconductor substrate that is approximately even with a height level of an upper surface of an uppermost conductive material of said first and second gate structures. 
     
     
         9 . The transistor device of  claim 7 , further comprising:
 a first sidewall spacer positioned adjacent opposing side surfaces of said gate separation structure; and   an epitaxial semiconductor material positioned on said at least one fin comprising each of said respective first and second spaced-apart active regions, said epitaxial semiconductor material abutting said first sidewall spacer.   
     
     
         10 . The transistor device of  claim 9 , further comprising a second sidewall spacer positioned adjacent sidewall surfaces of each of said first and second spaced-apart gate structures, said epitaxial semiconductor material further abutting said second sidewall spacers. 
     
     
         11 . The transistor device of  claim 7 , further comprising:
 a third active region positioned in said semiconductor substrate and spaced apart from said first active region, said third active region comprising at least one fin; and   a third gate structure positioned above said third active region and extending across said at least one fin of said third active region, said third gate structure being oriented substantially parallel to each of said first and second spaced-apart gate structures, wherein said first and third gate structures have end surfaces and wherein a portion of said gate separation structure extends between and abuts an entirety of said end surfaces of said first and third gate structures.   
     
     
         12 . The transistor device of  claim 11 , further comprising a fourth active region positioned in said semiconductor substrate and spaced apart from each of said second and third active regions, said fourth active region comprising at least one fin, wherein said third gate structure has a side surface that is positioned laterally adjacent to and spaced apart from a side surface of a gate structure extending across said at least one fin of said fourth active region, and wherein a further portion of said gate separation structure is positioned between said laterally adjacent side surfaces of said fourth gate structure and said gate structure extending across said at least one fin of said fourth active region. 
     
     
         13 . The transistor device of  claim 12 , wherein said gate structure extending across said at least one fin of said fourth active region comprises a portion of said second gate structure that extends continuously from said second active region and across said fourth active region. 
     
     
         14 . The transistor device of  claim 12 , wherein said gate separation structure has a substantially T-shaped configuration when viewed from above. 
     
     
         15 . The transistor device of  claim 7 , wherein each of said first and second spaced-apart gate structures comprise a high-k gate insulation layer and one or more metal layers positioned above said high-k gate insulation layer. 
     
     
         16 . A transistor device, comprising:
 a first active region positioned in a semiconductor substrate and comprising a first fin;   a first gate structure positioned above said first active region and extending across said first fin, said first gate structure having a first end surface and a first side surface;   a second active region positioned in said semiconductor substrate and spaced apart from said first active region, said second active region comprising a second fin;   a second gate structure positioned above said second active region and extending across said second fin, said second gate structure having a second end surface and a second side surface that is positioned laterally adjacent to and spaced apart from said first side surface of said first gate structure, wherein said second gate structure is oriented parallel to said first gate structure;   a third active region positioned in said semiconductor substrate and spaced apart from said first active region, said third active region comprising a third fin;   a third gate structure positioned above said third active region and extending across said third fin, said third gate structure having a third side surface and a third end surface that is positioned laterally adjacent to and spaced apart from said first end surface of said first gate structure, wherein said third gate structure is oriented parallel to said first and second gate structures;   a fourth active region positioned in said semiconductor substrate and spaced apart from said second and third active regions, said fourth active region comprising a fourth fin;   a fourth gate structure positioned above said fourth active region and extending across said fourth fin, said fourth gate structure having a fourth end surface that is positioned laterally adjacent to and spaced apart from said second end surface of said second gate structure and a fourth side surface that is positioned laterally adjacent to and spaced apart from said third side surface of said third gate structure, wherein said fourth gate structure is oriented parallel to said first, second, and third gate structures;   a gate separation structure having a substantially planar upper surface that is positioned at a greater height level above said semiconductor substrate than an upper surface of each of said first, second, third and fourth fins, said gate separation structure comprising:
 a first portion positioned between said laterally adjacent first and second side surfaces of said respective first and second gate structures; 
 a second portion positioned between said laterally adjacent first and third end surfaces of said respective first and third gate structures; 
 a third portion positioned between said laterally adjacent third and fourth side surfaces of said respective third and fourth gate structures; and 
 a fourth portion positioned between said laterally adjacent second and fourth side surfaces of said respective second and fourth gate structures. 
   
     
     
         17 . The transistor device of  claim 16 , wherein said gate separation structure has a substantially cross-shaped configuration when viewed from above. 
     
     
         18 . The transistor device of  claim 16 , wherein said second portion of said gate separation structure abuts an entirety of said first and third end surfaces of said respective first and third gate structures, and wherein said fourth portion of said gate separation structure abuts an entirety of said second and fourth end surfaces of said respective second and fourth gate structures. 
     
     
         19 . The transistor device of  claim 16 , further comprising:
 a first sidewall spacer positioned adjacent sidewall surfaces of said gate separation structure;   a second sidewall spacer positioned adjacent sidewall surfaces of each of said first, second, third and fourth gate structures; and   an epitaxial semiconductor material positioned on said first, second, third and fourth fins, said epitaxial semiconductor material abutting said first and second sidewall spacers.   
     
     
         20 . The transistor device of  claim 16 , wherein each of said first, second, third and fourth gate structures comprise a high-k gate insulation layer and one or more metal layers positioned above said high-k gate insulation layer.