Diode Biased ESD Protection Device and Method

Abstract

An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a semiconductor body of a first conductivity type;   a doped drain region of a second conductivity type disposed at a surface of the semiconductor body, the second conductivity type opposite to the first conductivity type;   a doped source region of the second conductivity type disposed at the surface of the semiconductor body and laterally spaced from the doped drain region by a region of the first conductivity type;   a gate, at least a portion of which insulatively overlies the region of the first conductivity type, wherein the gate further comprises   a region of the second conductivity type adjacent to the doped source region and the doped drain region, wherein the region of the second conductivity type forms a second diode region,   a region of the first conductivity type disposed adjacent to the region of the second conductivity type, wherein the region of the first conductivity type forms a first diode region,   a second region of the second conductivity type disposed adjacent to the region of the first conductivity type, and forming a third diode region, wherein the interface between the first diode region and the third diode region forms a second semiconductor junction;   a signal pad disposed on the semiconductor body, wherein the pad is coupled to the doped drain region; and   a diode coupled between the gate and source, wherein the diode comprises the first diode region of the first conductivity type and the second diode region of the second conductivity type, wherein an interface between the first and second diode regions forms a first semiconductor junction, and wherein the first diode region is coupled to the doped source region and the second diode region is coupled to the gate, wherein the semiconductor device is a electrostatic discharge (ESD) protection device.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the gate is isolated from all other nodes except the internal parasitic capacitance and the diode. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the gate further comprises a silicided region disposed over a portion of the second region of the second conductivity type, wherein the silicided region does not extend over the second semiconductor junction. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the gate further comprises a silicided region disposed over a portion of the region of the first conductivity type, wherein the silicided region does not extend over the first semiconductor junction. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the gate further comprises a silicided region touching a portion of the region of the first conductivity type, wherein the silicided region does not extend over the first semiconductor junction. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the gate further comprises an n-type, p-type or intrinsic region disposed adjacent to the region of the first conductivity type, and wherein the silicided region extends over at least a portion of the n-type, p-type, or intrinsic region. 
     
     
         7 . A semiconductor device comprising:
 a semiconductor body of a first conductivity type;   a doped drain region of a second conductivity type disposed at a surface of the semiconductor body, the second conductivity type opposite to the first conductivity type;   a doped source region of the second conductivity type disposed at the surface of the semiconductor body and laterally spaced from the doped drain region by a region of the first conductivity type;   a gate, at least a portion of which insulatively overlies the region of the first conductivity type;   a signal pad disposed on the semiconductor body, wherein the pad is coupled to the doped drain region;   a diode coupled between the gate and source, wherein the diode comprises a first diode region of the first conductivity type and a second diode region of the second conductivity type, wherein an interface between the first and second diode regions forms a first semiconductor junction, and wherein the first diode region is coupled to the doped source region and the second diode region is coupled to the gate; and   a third highly doped region of the second conductivity type disposed over a region of the semiconductor body, wherein the highly doped region of the first conductivity type forms the first diode region, and wherein the region of the semiconductor body forms the second diode region, wherein the semiconductor device is a electrostatic discharge (ESD) protection device.   
     
     
         8 . The semiconductor device of  claim 7 , wherein the gate is isolated from all other nodes except the internal parasitic capacitance and the diode, and the second diode. 
     
     
         9 . The semiconductor device of  claim 7 , further comprising a third doped region of the first conductivity type disposed over the second diode region, the third doped region of the first semiconductor type electrically connected to the doped source region. 
     
     
         10 . A semiconductor device comprising:
 a semiconductor body of a first conductivity type;   a doped drain region of a second conductivity type disposed at a surface of the semiconductor body, the second conductivity type opposite to the first conductivity type;   a doped source region of the second conductivity type disposed at the surface of the semiconductor body and laterally spaced from the doped drain region by a region of the first conductivity type;   a gate, at least a portion of which insulatively overlies the region of the first conductivity type;   a signal pad disposed on the semiconductor body, wherein the pad is coupled to the doped drain region;   a diode coupled between the gate and source, wherein the diode comprises a first diode region of the first conductivity type and a second diode region of the second conductivity type, wherein an interface between the first and second diode regions forms a first semiconductor junction, and wherein the first diode region is coupled to the doped source region and the second diode region is coupled to the gate; and   a third doped region of the first conductivity type disposed adjacent to a third highly doped region of the second conductivity type, the third highly doped region of the first conductivity type forming the first diode region and the third doped region of the second conductivity type forming the second diode region, wherein the semiconductor device is a electrostatic discharge (ESD) protection device.   
     
     
         11 . The semiconductor device of  claim 10 , wherein the gate is isolated from all other nodes except the internal parasitic capacitance and the diode, and the second diode. 
     
     
         12 . The semiconductor device of  claim 10 , wherein the doped drain region, the doped source region, and the gate form a PMOS transistor. 
     
     
         13 . The semiconductor device of  claim 10 , wherein the doped drain region, the doped source region, and the gate form a NMOS transistor. 
     
     
         14 . The semiconductor device of  claim 10 , wherein the doped drain region is coupled to a ground potential. 
     
     
         15 . The semiconductor device of  claim 10 , wherein the source is coupled to a reference potential. 
     
     
         16 . The semiconductor device of  claim 10 , wherein the doped drain region, the doped source region, and the gate form a MOS transistor, and wherein no additional external capacitor is placed between the gate and doped drain of the MOS transistor. 
     
     
         17 . The semiconductor device of  claim 16 , wherein the semiconductor device is configured to be triggered via the internal parasitic capacitance of the MOS transistor and without a capacitor external to the MOS transistor.