Static random access memory with reduced write power

Abstract

A static random access memory (SRAM) features reduced write cycle power consumption. The SRAM includes an array of static storage cells and a write controller. The array of static storage cells is accessible via a plurality of word lines and a plurality of bit lines, and is arranged to access multiple bits via each of the word lines. The write controller controls writing to the static storage cells. The write controller is configured to perform consecutive writes to a plurality of addresses associated with a same one of the word lines, and to, in conjunction with the consecutive writes, perform fewer precharges of the bit lines than consecutive writes.

What is claimed is: 
     
         1 . A memory, comprising:
 an array of static storage cells accessible via a plurality of word lines and a plurality of bit lines, and arranged to access multiple bits via each of the word lines;   a write controller that controls writing to the static storage cells, the write controller configured to:
 perform consecutive writes to a plurality of addresses associated with a same one of the word lines; and 
 in conjunction with the consecutive writes, perform fewer precharges of the bit lines than consecutive writes. 
   
     
     
         2 . The memory of  claim 1 , wherein the write controller is configured to perform only a single precharge of the bit lines in conjunction with the consecutive writes. 
     
     
         3 . The memory of  claim 1 , wherein the write controller is configured to perform only a single precharge of the bit lines per assertion of a signal to the memory that indicates a write operation is to be performed. 
     
     
         4 . The memory of  claim 1 , wherein the write controller is configured to:
 store an indication of which one of the word lines was last asserted; and   perform a precharge of the bit lines based on one of the word lines currently asserted being different from the one of the word lines that was last asserted.   
     
     
         5 . The memory of  claim 1 , wherein the write controller is configured to perform a precharge of the bit lines at a start of the consecutive writes. 
     
     
         6 . The memory of  claim 1 , wherein the write controller is configured to perform a precharge of the bit lines at an end of the consecutive writes. 
     
     
         7 . The memory of  claim 1 , wherein the write controller is configured to perform a precharge of the bit lines based on time since a last access of the storage cells via the same one of the word lines exceeding a predetermined time. 
     
     
         8 . An integrated circuit, comprising:
 a static random access memory (SRAM), comprising:
 an array of storage cells arranged as rows and columns, and comprising word lines that correspond to the rows and bit lines that correspond to the columns; and 
 a write controller to manage writing to the storage cells, the write controller configured to:
 identify consecutive writes to storage cells accessed via a same one of the word lines; and 
 precharge the bit lines on fewer than all of the consecutive writes. 
 
   
     
     
         9 . The integrated circuit of  claim 8 , wherein the write controller is configured to precharge the bit lines only once in conjunction with the consecutive writes. 
     
     
         10 . The integrated circuit of  claim 8 , wherein the write controller is configured to precharge the bit lines only once per assertion of a signal to the SRAM that indicates a plurality of consecutive writes is to be performed. 
     
     
         11 . The integrated circuit of  claim 8 , wherein the write controller is configured to:
 store an indication of which one of the word lines was last asserted; and   perform a precharge of the bit lines based on one of the word lines currently asserted being different from the one of the word lines that was last asserted.   
     
     
         12 . The integrated circuit of  claim 8 , wherein the write controller is configured to perform a precharge of the bit lines at a start of the consecutive writes. 
     
     
         13 . The integrated circuit of  claim 8 , wherein the write controller is configured to perform a precharge of the bit lines at an end of the consecutive writes. 
     
     
         14 . The integrated circuit of  claim 8 , wherein the write controller is configured to perform a precharge of the bit lines based on time since a last access of the storage cells via the same one of the word lines exceeding a predetermined time. 
     
     
         15 . A static random access memory (SRAM), comprising:
 an array of storage cells arranged as rows and columns, and comprising word lines that correspond to the rows and bit lines that correspond to the columns; and   a write controller to manage writing to the storage cells, the write controller configured to:
 identify consecutive writes to storage cells accessed via a same one of the word lines; and 
 precharge the bit lines no more than once during the consecutive writes. 
   
     
     
         16 . The SRAM of  claim 15 , wherein the write controller is configured to perform only a single precharge of the bit lines per assertion of a signal to the memory that indicates that consecutive writes are to be performed. 
     
     
         17 . The SRAM of  claim 15 , wherein the write controller is configured to:
 store an indication of which one of the word lines was last asserted; and   perform a precharge of the bit lines based on one of the word lines currently asserted being different from the one of the word lines that was last asserted.   
     
     
         18 . The SRAM of  claim 15 , wherein the write controller is configured to perform a precharge of the bit lines at a start of the consecutive writes. 
     
     
         19 . The SRAM of  claim 15 , wherein the write controller is configured to perform a precharge of the bit lines at an end of the consecutive writes. 
     
     
         20 . The SRAM of  claim 15 , wherein the write controller is configured to perform a precharge of the bit lines based on time since a last access of the storage cells via the same one of the word lines exceeding a predetermined time.