Semiconductor integrated circuit device

Abstract

An output signal characteristic of a differential amplifier circuit is improved. When an input data signal becomes ‘Low’, current flowing through a first transistor will decrease and potential at a connection (a node) between a first resistor and a second resistor will increase. This potential is input (negatively fed back) to the gate of a second transistor, and because this gate potential increases, a tail current amount is adjusted in an increasing direction. When the input data signal becomes ‘High’, the current of the first transistor increases and thus the potential at the node decreases. Thus, the gate potential (negative feedback) of the second transistor decreases, and the tail current amount is adjusted in a decreasing direction. Thus, in the rising and falling of an input waveform, the difference in a delay time with respect to the output waveform decreases, respectively.

1 - 16 . (canceled) 
     
     
         17 . A memory device, comprising:
 a plurality of external terminals; and   a plurality of differential amplifier circuits, each being provided for a corresponding one of the external terminals, wherein each of the differential amplifier circuits comprises:
 a first differential input section receiving a input signal from the corresponding one of the external terminals; 
 a second differential input section receiving a reference voltage; and 
 a tail current source connected commonly to the first differential input section and the second differential section and receiving a current of the first differential input section and a current of the second differential input section, and 
   wherein a current on the first differential input section side is detected and fed back to the tail current source so as to control a tail current flowing through the tail current source.   
     
     
         18 . The memory device according to  claim 17 , wherein the current on the first differential input section side is converted to a voltage by means of a resistor and the voltage, to which the resistor has converted, is fed back to the tail current source. 
     
     
         19 . The memory device according to  claim 17 , further comprising:
 a first and a second transistor constituting the first differential input section and the second differential input section, respectively;   a third transistor used as the tail current source of the first and the second transistor; and   a current detection section detecting a current flowing through the first transistor,   wherein the third transistor controls a current amount of the tail current in the tail current source based on a current which the current detection section detects.   
     
     
         20 . The memory device according to  claim 19 ,
 wherein the current detection section includes a resistor for converting the current flowing through the first transistor to a voltage, and   wherein the third transistor has a gate to which the voltage is supplied.   
     
     
         21 . A memory device comprising:
 a plurality of external terminals each receiving data signal as data; and   a plurality of differential amplifier circuits, each being provided for a corresponding one of the external terminals, wherein each of the differential amplifier circuits comprises:
 a first differential input section including a first transistor coupled to a first node, the first transistor having a gate connected to the corresponding one of the external terminals; 
 a second differential input section including a second transistor coupled between a first power supply voltage line and the first node, the second transistor having a gate to which a reference voltage is applied; 
 a tail current source including a third transistor coupled between the first node and a second power supply line; and 
 a resistor having a first and a second end, the first end coupled to the first power supply line and the second end coupled to the first transistor, 
   wherein the third transistor has a gate coupled to the second end of the resistor.   
     
     
         22 . A memory device, comprising:
 a first external terminal receiving a first signal of differential signal;   a second external terminal receiving a second signal that is an inverted signal of the first signal of the differential signals;   a first differential amplifier circuit including a first differential input section receiving the first signal from the first external terminal and a second differential input section receiving a reference voltage, the first differential amplifier circuit carrying out a differential amplification of the first signal and the reference voltage; and   a second differential amplifier circuit including a third differential input section receiving the second signal from the second external terminal and a fourth differential input section receiving the reference voltage, the second differential amplifier circuit carrying out a differential amplification of the second signal and the reference voltage,   wherein the first differential amplifier circuit detects a current on the first differential input section side, and feeds this back to a first tail current source of the first differential amplifier circuit to control a tail current in the first tail current source, and   wherein the second differential amplifier circuit detects a current on the third differential input section side, and feeds this back to a second tail current source of the second differential amplifier circuit to control a tail current in the second tail current source.   
     
     
         23 . The memory device according to  claim 22 , further comprising a delay time adjustment circuit, to which a first output signal output from the first differential amplifier circuit and a second output signal from the second differential amplifier are input, and which adjusts so that a delay difference between the first output signal and the second output signal is substantially eliminated, and outputs the first output signal and the second output signal. 
     
     
         24 . The memory device according to  claim 22 ,
 wherein the first differential amplifier circuit includes a first and a second transistor constituting the first differential input section and the second differential input section, respectively, a third transistor coupled to the first and the second transistor to constitute the first tail current source, and a first current detection section detecting a current flowing through the first transistor,   wherein the third transistor controls a current amount of a tail current flowing through the third transistor based on the current which the first current detection section detects,   wherein the second differential amplifier circuit includes a fourth and a fifth transistor constituting the third differential input section and the fourth differential input section, respectively, a sixth transistor coupled to the fourth and the fifth transistor to constitute the second tail current source, and a second current detection section detecting a current flowing through the fourth transistor,   wherein the sixth transistor controls a current amount of a tail current flowing through the sixth transistor based on the current which the second current detection section detects.