Low Power Shift Register

Abstract

A clock control circuit for a parallel in, serial out (PISO) shift register helps save power. The clock control circuit selectively clocks the shift register as it converts a parallel input to a serial output. For example, the clock control circuit may provide clock signals to the flip flops (or other buffers) in the shift register that will receive data elements provided with the parallel input. However, the clock control circuit withholds clock signals from flip flops that will not receive data elements provided with the parallel input, or that have already been received by a particular flip flop. As the parallel loaded input elements propagate serially through the shift register, on each clock cycle an additional memory no longer needs to be clocked. The memory no longer needs to be clocked because that memory has already propagated its loaded input element to the following memory, and no further element provided in the N element parallel loaded data is incoming.

What is claimed is: 
     
         1 . A device comprising:
 a multiple-bit memory comprising serially connected elements; and   clock circuitry configured to withhold clock signals from an increasing number of the serially connected elements as a parallel-to-serial conversion operation proceeds through the multiple-bit memory.   
     
     
         2 . A device comprising:
 memory elements coupled together to perform a data conversion operation on a multiple-bit input; and   clock circuitry coupled to the memory elements, the clock control circuitry configured to:   generate clock signals for the memory elements for performing the data conversion operation on the multi-bit input; and   determine which clock signals to generate according to which memory elements hold data from the multi-bit input yet to be converted.   
     
     
         3 . A method comprising:
 generating a decreasing number of clock signals to serially coupled memory stages as a parallel-to-serial conversion operation progresses through the serially coupled memory stages.