Memory control and data processing using memory address generation based on differential addresses

Abstract

A memory control device that transfers data from an external memory to a data processing unit having plural processing mechanisms, includes an absolute address storage unit that stores an absolute address serving as a common reference value in a given data transfer period; a differential address storage unit that stores plural differential addresses therein; a differential address selection unit that selects any one of the plurality of differential addresses in a given order; a memory address generation unit that combines any differential address selected by the differential address selection unit with the absolute address to generate a memory address; and a data transfer unit that inputs the memory address generated by the memory address generation unit to the external memory, reads the data from the memory address, and transfers the data to the data processing unit.

What is claimed is: 
     
         1 . A data processing device, comprising:
 a Central Processing Unit (CPU);   a memory;   a SIMD (Single Instruction Multiple Data) Processor; and
 a bus through which the CPU, the memory and the SIMD processor are coupled each other; 
   
       wherein the SIMD Processor comprising: 
       a data Processing unit having a plurality of processing elements (PEs); and 
       a control processor (CP) that controls the respective PEs; 
       wherein the control processor include: 
       an absolute address register that stores an absolute address serving as a common reference value in a given data transfer period therein; 
       a first differential address register that stores a plurality of first differential addresses therein, each of the differential addresses indicating a difference between a read address and the absolute address; 
       a first pointer register that designates the plurality of first differential addresses in a given order;
 a memory address generator circuit that combines any differential address selected by the first pointer register with the absolute address to generate a memory address; and 
 a data transfer circuit that inputs the memory address generated by the memory address generator circuit to the memory, and reads and transfers data from the memory address. 
 
     
     
         2 . An image processing system, comprising:
 an image pickup device that picks up an image and stores the image in the memory;   the data processing device according to  claim 1 , which reads image data temporarily stored in the memory to conduct given data processing; and   an image display device that displays the image data that has been subjected to the given data processing by the data processing device.   
     
     
         3 . The data processing device according to  claim 1 , wherein the control processor further include:
 a second differential address register that stores a plurality of second differential addresses therein, each of the differential addresses indicating a difference between a read address and the absolute address;
 a second pointer register that designates the plurality of second differential address in the given order; 
   and,
 the memory address generator circuit that combines any differential address selected by the first and second pointer registers with the absolute address to generate a memory address. 
   
     
     
         4 . An image processing system, comprising:
 an image pickup device that picks up an image and stores the image in the memory;   the data processing device according to  claim 3 , which reads image data temporarily stored in the memory to conduct given data processing; and   an image display device that displays the image data that has been subject to the given data processing by the data processing device.   
     
     
         5 . A semiconductor integrated circuit, comprising
 a Central Processing Unit (CPU);   a memory;   a SIMD (Single Instruction Multiple Data) Processor; and   a bus through which the CPU, the memory and the SIMD processor are coupled each other;   wherein the SIMD Processor comprising:
 a data Processing unit having a plurality of processing elements (Pes); and 
 a control processor (CP) that controls the respective Pes; 
   wherein the control processor include:   an absolute address register that stores an absolute address serving as a common reference value in a given data transfer period therein;   a first differential address register that stores a plurality of first differential addresses therein, each of the differential addresses indicating a difference between a read address and the absolute address;   a first pointer register that designates the plurality of first differential addresses in a given order;
 a memory address generator circuit that combines any differential address selected by the first pointer register with the absolute address to generate a memory address; and 
 a data transfer circuit that inputs the memory address generated by the memory address generator circuit to the memory, and reads and transfers data from the memory address. 
   
     
     
         6 . The semiconductor integrated circuit according to  claim 5 ,
 wherein the control processor further include:   a second differential address register that stores a plurality of second differential addresses therein, each of the differential addresses indicating a difference between a read address and the absolute address;
 a second pointer register that designates the plurality of second differential addresses in the given order; and, 
 the memory address generator circuit that combines any differential address selected by the first and second pointer registers with the absolute address to generate a memory address.