Signal processing device and semiconductor device

Abstract

A signal processing device includes a signal processor that receives an input stream including a plurality of pieces of input data, execute a predetermined task on stream data, and outputs an output stream including a plurality of pieces of output data. The signal processing device includes a pointer indicating position information of data in the stream data according to progress of processing by the signal processor. When priority processing of a second task is requested during execution of a first task, the signal processing device executes the second task after saving a value held by the pointer. Based on the saved pointer value the signal processing device obtains position information, in the output stream, of output data to be outputted in the first task, and obtains position information, in the input stream, of input data.

What is claimed is: 
     
         1 . A signal processing device comprising:
 a signal processor that receives an input stream comprised of a plurality of pieces of input data, execute a predetermined task on stream data, and outputs an output stream comprised of a plurality of pieces of output data,   wherein the signal processing device comprises a pointer indicating position information of data in the stream data according to progress of processing by the signal processor,   wherein when priority processing of a second task is requested during execution of a first task, the signal processing device executes the second task after saving a value held by the pointer, and   wherein based on the saved pointer value the signal processing device obtains position information, in the output stream, of output data to be outputted in the first task, and obtains position information, in the input stream, of input data that needs to be inputted to the signal processor to calculate the output data to be outputted.   
     
     
         2 . The signal processing device according to  claim 1 , further comprising a memory for storing the input stream and writing the output stream and a task switching control unit,
 the signal processor comprising an input address register and an output address register,   wherein the input address register holds an address, in the memory, of the input data which the signal processor reads, and the output address register holds an address, in the memory, of the output data which the signal processor writes.   
     
     
         3 . The signal processing device according to  claim 2 , wherein upon completion of the second task, the task switching control unit calculates position information in the output stream of the output data to be outputted next in the first task, with an output position function based on the saved pointer value, calculates an address in the memory of the output data to be outputted next, with an output address function based on an output of the output position function, and writes the address to the output address register, and
 wherein the task switching control unit calculates position information in the input stream of the head input data, with an input position function based on the saved pointer value, calculates an address in the memory of the head input data, with an input address function, and writes the address to the input address register.   
     
     
         4 . The signal processing device according to  claim 3 , wherein the stream data is image data, and the pointer holds a pixel number, a line number, a block number, a frame number, or a combination thereof in the output stream of output data which has been outputted by the signal processor,
 wherein the output position function calculates a pixel number, a line number, a block number, a frame number, or a combination thereof of the output data to be outputted next in the first task based on the saved pointer value, and   wherein the input position function calculates a pixel number, a line number, a block number, a frame number, or a combination thereof in the input stream of the head input data based on the saved pointer value.   
     
     
         5 . The signal processing device according to  claim 3 , 
       wherein the stream data is image data, and the pointer holds a pixel number, a line number, a block number, a frame number, or a combination thereof in the input stream of input data which has been outputted by the signal processor,
 wherein the output position function calculates a pixel number, a line number, a block number, a frame number, or a combination thereof of the output data to be outputted next in the first task based on the saved pointer value, and 
 wherein the input position function calculates a pixel number, a line number, a block number, a frame number, or a combination thereof in the input stream of the head input data based on the saved pointer value. 
 
     
     
         6 . The signal processing device according to  claim 3 , 
       wherein the first task is a signal processing task including a plurality of pieces of signal processing in which an output stream obtained by performing signal processing on the input stream by the signal processor is an input stream of next signal processing in sequence,
 wherein each signal processing has a part position function for outputting position information of head input data of all input data that needs to be inputted to the signal processor to calculate output data to be outputted next, and 
 wherein the saved pointer value is inputted to a part position function corresponding to signal processing executed last, in the first task, of the plurality of pieces of signal processing, and an output of a part position function corresponding to signal processing executed subsequently, in the first task, of the plurality of pieces of signal processing is inputted to a part position function corresponding to signal processing executed immediately previously, thus performing nesting in sequence to configure the input position function. 
 
     
     
         7 . The signal processing device according to  claim 6 , 
       wherein the stream data is image data, and signal processing performed by the signal processor is n×n spatial filtering (n is an odd number equal to or greater than three),
 wherein a part position function corresponding to the spatial filtering inputs a line number whose output is completed and outputs a line number (n−1)/2 line before the saved pointer value, and 
 wherein the input position function includes the part position function corresponding to the spatial filtering. 
 
     
     
         8 . A semiconductor device, comprising:
 a processor; and   a memory connected with the processor,   wherein the processor comprises:
 a processing module; and 
 a processing control unit communicating with the processing module, 
 wherein the processing module receives an input stream comprised of a plurality of pieces of input data, executes predetermined processing on stream data, and outputs an output stream comprised of a plurality of pieces of output data, 
 wherein the processing control unit comprises a pointer indicating position information, in the stream data, of processing data according to progress of processing by the processing module, reads the input data from the memory by specifying a read address and inputs the input data to the processing module, and outputs the output data of the processing module to the memory by specifying a write address, 
 wherein when priority processing of a second task is requested during execution of a first task, the processor allows the processor to execute the second task after saving a value held by the pointer. 
   
     
     
         9 . The semiconductor device according to  claim 8 , wherein when the priority task processing is requested, the processor saves a pointer value, and at a time of return, based on the saved pointer value,
 wherein the processor obtains position information of the output stream data to be outputted next in a returned task, obtains position information, in an input stream, of head input data of all input data that needs to be inputted to the processor to calculate the data, and resumes the processing.   
     
     
         10 . The semiconductor device according to  claim 8 , wherein upon completion of the second task, the processor returns the saved pointer value, and based on the returned pointer value, obtains an address in the memory to store output data to be outputted next in the first task and sets the write address, and obtains an address for storing head input data of all input data that needs to be inputted to the processor to calculate the output data to be outputted next and sets the read address. 
     
     
         11 . The semiconductor device according to  claim 8 , 
       wherein the processing control unit comprises a read address register for holding the read address, a write address register for holding the write address, and a pointer register for holding the pointer value,
 wherein when the priority processing is requested, the processor saves a first value of the pointer register into the memory, 
 wherein upon completion of the second task, the processor returns the first value from the memory to the pointer register, 
 wherein the processor calculates position information in the output stream of the output data to be outputted next in the first task, with an output position function based on the first value, calculates an address in the memory of the output data to be outputted next in the first task, with an output address function based on an output of the output position function, and writes the address to the write address register, and 
 wherein the processor calculates position information in the input stream of the head input data, with an input position function based on the first value, calculates an address in the memory of the head input data, with an input address function, and writes the address to the read address register. 
 
     
     
         12 . The semiconductor device according to  claim 8 , 
       wherein the processing control unit comprises a read address register for holding the read address, a write address register for holding the write address, and a pointer register for holding the pointer value,
 wherein when the priority processing is requested, the processor saves a first value of the pointer register into the memory. 
 
     
     
         13 . The semiconductor device according to  claim 8 , 
       wherein the processing control unit further comprises a parameter register,
 wherein the processing module executes signal processing in accordance with a parameter held by the parameter register, and 
 wherein when the priority processing is requested, the processor discards a value held by the parameter register without save, and writes a parameter for allowing the processing module to execute the second task to the parameter register. 
 
     
     
         14 . The semiconductor device according to  claim 13 , 
       wherein the memory stores the parameter for each processing content of processing executed by the processing module, and
 wherein when a processing task is requested, the processor reads the parameter corresponding to processing content of the processing task from the memory, and writes the parameter to the parameter register. 
 
     
     
         15 . A method of a semiconductor device including a CPU (Central Processing Unit), a memory, a signal processing unit including a signal processing module and a signal processing control unit, and a context processing unit that that are electrically communicating, the method comprising:
 receiving, by the signal processing module, an input stream comprised of a plurality of pieces of input data;   executing, by the signal processing module, a predetermined signal processing on stream data, and outputs an output stream comprised of a plurality of pieces of output data,   wherein the signal processing control unit comprises a pointer indicating position information, in the stream data, of processing data according to progress of processing by the signal processing module, reads the input data from the memory by specifying a read address and inputs the input data to the signal processing module, and outputs the output data of the signal processing module to the memory by specifying a write address, and   wherein the context processing unit comprises a context position storage unit and a restoration unit;   allowing, by the context processing unit, to execute, by the signal processing unit, the second task after saving a value held by the pointer into the context position storage unit, when priority processing of a second task is requested during execution of a first task,   upon completion of the second task, returning, by the context processing unit, the saved pointer value; and   obtaining, by the restoration unit, an address in the memory to store output data to be outputted next in the first task and sets the write address based on the returned pointer value.   
     
     
         16 . The method according to  claim 15 , further comprising of obtaining an address for storing head input data of all input data that needs to be inputted to the signal processing unit to calculate the output data to be outputted next and sets the read address. 
     
     
         17 . The method according to  claim 16 , 
       wherein the signal processing control unit comprises a read address register for holding the read address, a write address register for holding the write address, and a pointer register for holding the pointer value,
 wherein when the priority processing is requested, the context processing unit saves a first value of the pointer register into the context position storage unit, 
 wherein upon completion of the second task, the context processing unit returns the first value from the context position storage unit to the pointer register, 
 wherein the restoration unit calculates position information in the output stream of the output data to be outputted next in the first task, with an output position function based on the first value, calculates an address in the memory of the output data to be outputted next in the first task, with an output address function based on an output of the output position function, and writes the address to the write address register, and 
 wherein the restoration unit calculates position information in the input stream of the head input data, with an input position function based on the first value, calculates an address in the memory of the head input data, with an input address function, and writes the address to the read address register. 
 
     
     
         18 . The method according to  claim 15 , 
       wherein the signal processing control unit further comprises a parameter register,
 wherein the signal processing module executes signal processing in accordance with a processing parameter held by the parameter register, and 
 wherein when the priority processing is requested, the restoration unit discards a value held by the parameter register without save, and writes a processing parameter for allowing the signal processing module to execute the second task to the parameter register. 
 
     
     
         19 . The method according to  claim 18 , 
       wherein the memory stores the processing parameter for each content of processing executed by the signal processing module, and
 wherein when a task is requested, the restoration unit transfers the processing parameter corresponding to processing content of the task from the memory to the parameter register. 
 
     
     
         20 . The method according to  claim 15 , 
       wherein when priority processing of a second task is requested during execution of a first task, the context processing unit associates and saves a context number of the first task with a value held by the pointer into the context position storage unit, and
 wherein upon completion of the second task, the restoration unit sets the write address and the read address, based on the saved context number and the returned pointer value.