Embedded system development

Abstract

A computer-implemented method of automatically generating an embedded system on the basis of an original computer program, comprising analyzing the original computer program, comprising a step of compiling the original computer program into an executable to obtain data flow graphs with static data dependencies and a step of executing the executable using test data to provide dynamic data dependencies as communication patterns between load and store operations of the original computer program, and a step of transforming the original computer program into an intermediary computer program that exhibits multi-threaded parallelism with inter-thread communication, which comprises identifying at least one static and/or dynamic data dependency that crosses a thread boundary and converting said data dependency into a buffered communication channel with read/write access.

1 . A computer-implemented method of automatically generating an embedded system on the basis of an original computer program, which embedded system provides a parallelized hardware and software implementation of the original computer program, which parallelized implementation satisfies one or more predetermined criteria regarding hardware constraints of the embedded system, the method comprising
 a step of analyzing the original computer program, comprising a step of compiling the original computer program into an executable to obtain a control data flow graph with static data dependencies and static data types, said control data flow graph being a reducible control data flow graph, in which each loop in said graphs is identified by exactly one loop entry node, and a step of executing the executable on a host computer using test data, comprising observing a working memory of the host computer during the executing of the executable, obtaining dynamic analysis data,   said reducible control data flow graph comprising one or more loops each having an entry edge and an exit edge, where each loop is provided with loop entry control nodes for each entry edge, configured for creating a token on its output for every token that arrives at its input, each loop entry control node being accompanied by a loop exit control node, being a control mechanism to ensure that the loop exit edge is only activated on performing the actual loop exit,   a step of transforming, using the reducible control data flow graph and the dynamic analysis data, the original computer program   into an intermediary computer program that exhibits multi-threaded parallelism with inter-thread communication, having a distributed and pipelined execution control structure, the intermediary computer program employing a process network representing an assignment of program elements to processes or threads and an assignment of read and write operations in the transformed intermediary computer program to buffered communication channels between processes using said process network, and   a step of building the parallelized hardware and software implementation from the transformed intermediary computer program, comprising a step of compiling the transformed intermediary computer program to obtain the software implementation, wherein the parallelized hardware and software implementation are generated via a generate step that generates an architecture description and involves an acceleration step to convert the program function into register transfer level, which are then subjected to an integrate process, and wherein the parallelized hardware and software implementation exhibit an implementation of the process network and operate in parallel without further dynamic data dependency analysis.   
     
     
         2 - 14 . (canceled) 
     
     
         15 . A computer system for automatically generating an embedded system on the basis of an original computer program, which embedded system provides a parallelized hardware and software implementation of the original computer program, which parallellized implementation satisfies one or more predetermined criteria regarding hardware constraints of the embedded system comprising: a processor, a memory having code executed by the processor to perform operations, the operations comprising:
 a step of analyzing the original computer program, comprising a step of compiling the original computer program into an executable to obtain a control data flow graph with static data dependencies and static data types, said control data flow graph being a reducible control data flow graph, in which each loop in said graphs is identified by exactly one loop entry node, and a step of executing the executable on a host computer using test data, comprising observing a working memory of the host computer during the executing of the executable, obtaining dynamic analysis data,   said reducible control data flow graph comprising one or more loops each having an entry edge and an exit edge, where each loop is provided with loop entry control nodes for each entry edge, configured for creating a token on its output for every token that arrives at its input, each loop entry control node being accompanied by a loop exit control node, being a control mechanism to ensure that the loop exit edge is only activated on performing the actual loop exit,   a step of transforming, using the reducible control data flow graph and the dynamic analysis data, the original computer program into an intermediary computer program that exhibits multi-threaded parallelism with inter-thread communication, having a distributed and pipelined execution control structure, the intermediary computer program employing a process network representing an assignment of program elements to processes or threads and an assignment of read and write operations in the transformed intermediary computer program to buffered communication channels between processes using said process network, and   a step of building the parallelized hardware and software implementation from the transformed intermediary computer program, comprising a step of compiling the transformed intermediary computer program to obtain the software implementation, wherein the parallelized hardware and software implementation are generated via a generate step that generates an architecture description and involves an acceleration step to convert the program function into register transfer level, which are then subjected to an integrate process, and wherein the parallelized hardware and software implementation exhibit an implementation of the process network and operate in parallel without further dynamic data dependency analysis.   
     
     
         16 . The method of  claim 1 , in which the loop entry and exit control nodes comprise functionality for passing of single-bit control tokens denoting availability of data in local registers. 
     
     
         17 . The method of claim  2 , in which the nodes each have only one token buffer for the combined set of output edges. 
     
     
         18 . The method of  claim 1 , in which the loop entry and exit control nodes comprise functionality for passing control tokens over edges of the reducible control data flow graph, each control token being configured to distinguish on token presence or absence, and if present on a boolean token value, to control the execution in the reducible control data flow graph and maintain token ordering in pipelined execution. 
     
     
         19 . The method of claim  2 , in which the loop entry and exit control nodes comprise functionality for passing control tokens over edges of the reducible control data flow graph, each control token being configured to distinguish on token presence or absence, and if present on a boolean token value, to control the execution in the reducible control data flow graph and maintain token ordering in pipelined execution. 
     
     
         20 . The method of  claim 1 , in which the reducible control data flow graph is obtained by generating a generic control data flow graph reducible and converting said generic control data flow graph into a reducible control data flow graph. 
     
     
         21 . The method of claim  2 , in which the reducible control data flow graph is obtained by generating a generic control data flow graph reducible and converting said generic control data flow graph into a reducible control data flow graph.