US2016065729A1PendingUtilityA1

Dual-source hybrid cancellation scheme

Assignee: IKANOS COMMUNICATIONS INCPriority: Sep 2, 2014Filed: Sep 2, 2015Published: Mar 3, 2016
Est. expirySep 2, 2034(~8.1 yrs left)· nominal 20-yr term from priority
Inventors:James May
H04M 3/18H04L 25/0266H04M 11/062H04M 3/007
34
PatentIndex Score
0
Cited by
0
References
0
Claims

Abstract

Embodiments of the invention relate to methods and apparatuses for performing hybrid rejection that overcome various shortcomings of the prior art. In one embodiment, the transformer's receive winding is stacked on top of the transmit winding, the two being wired in series and in phase. Z2 is scaled by approximately half so as to maintain the same receive gain. In another embodiment, rather than stacking the receive and transmit windings for series summation, they are each used as independent sources into the summing junction of the receive amp. If Z2 and Z3 are equal, then an equal proportion of V1 and V2 are summed.

Claims

exact text as granted — not AI-modified
What is claimed: 
     
         1 . A hybrid circuit for improving hybrid rejection, comprising:
 a transmit port for transmitting a transmit signal;   a receive port for receiving a receive signal;   a differential amplifier, wherein the output of the differential amplifier is connected to the receive port;   a transformer having a receive winding corresponding to the receive port and a transmit winding corresponding to the transmit port, wherein the receive winding is stacked on top of the transmit winding.   
     
     
         2 . The hybrid circuit of  claim 1 , wherein the transmit winding and the receive winding are wired in series and in phase around a single core. 
     
     
         3 . The hybrid circuit of  claim 1 , wherein the first end of the receive winding is connected to a summing junction of the differential amplifier through an impedance Z2, the other end of the receive winding is connected to a junction of the first end of the transmit winding and a back matching impedance Zsrc which in turn is connected to the transmit signal at the transmit port, and a signal with opposite polarity to the transmit signal is connected to the summing junction of the differential amplifier through an impedance Z1. 
     
     
         4 . The hybrid circuit of  claim 3 , wherein Z2 is scaled by approximately half of Z1 so as to maintain the same receive gain. 
     
     
         5 . The hybrid circuit of  claim 2 , wherein the receive winding is split into two halves and connected on either side of the transmitting winding. 
     
     
         6 . A hybrid circuit for improving hybrid rejection, comprising:
 a transmit port for transmitting a transmit signal;   a receive port for receiving a receive signal;   a differential amplifier, wherein the output of the differential amplifier is connected to the receive port;   a transformer having a receive winding corresponding to the receive port and a transmit winding corresponding to the transmit port, wherein the transmit winding and the receive winding are wired separately.   
     
     
         7 . The hybrid circuit of  claim 6 , wherein the transmit winding and the receive winding are wired but in phase around a single core. 
     
     
         8 . The hybrid circuit of  claim 6 , wherein the first end of the receive winding is connected to a summing junction of the differential amplifier through a variable impedance Z2, the other end of the receive winding is connected to the ground, the first end of the transmit winding is connected to a junction of a back matching impedance Zsrc and a variable impedance Z3, the Zsrc is in turn connected to the transmit port, the Z3 is in turn connected to the summing junction of the differential amplifier, and a signal with opposite polarity of the transmit signal is connected to the summing junction of the differential amplifier through an impedance Z1. 
     
     
         9 . The hybrid circuit of  claim 8 , wherein the ratio of Z2 and Z3 are adjustable to allow an arbitrary frequency point within a predefined droop/tilt range to be nulled at the receive port. 
     
     
         10 . The hybrid circuit of  claim 8 , wherein the Z2 and Z3 are variable resistors. 
     
     
         11 . The hybrid circuit of  claim 8 , wherein the Z2 and Z3 can be fixed. 
     
     
         12 . The hybrid circuit of  claim 8 , wherein the variable resistances of Z2 and Z3 are programmable to allow for best hybrid rejection for a given frequency, line conditions and component variations.

Join the waitlist — get patent alerts

Track US2016065729A1 — get alerts on status changes and closely related new filings.

We store only your email — no account needed. See our privacy policy.