Semiconductor device

Abstract

A semiconductor device includes a synthesizer, a phase locked loop (PLL) circuit, and a clock generating unit which is coupled to a crystal oscillator and generates an oscillation signal, and supplies the oscillation signal to the synthesizer and PLL circuit as a clock signal.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a synthesizer;   a phase locked loop (PLL) circuit; and   a clock generating unit which is coupled to a crystal oscillator and generates an oscillation signal, and supplies the oscillation signal to the synthesizer and PLL circuit as a clock signal.   
     
     
         2 . The semiconductor device of  claim 1 , further comprising:
 a radio frequency unit;   an analog/digital converter; and   a digital baseband,   wherein an output of the synthesizer is supplied to the radio frequency unit, and an output of the PLL circuit is supplied to the analog/digital converter and the digital baseband.   
     
     
         3 . The semiconductor device of  claim 1 , wherein the clock generating unit comprises:
 an oscillation circuit which generates the oscillation signal; and   an effective value measuring circuit which measures an effective value of the oscillation signal.   
     
     
         4 . The semiconductor device of  claim 3 , wherein the oscillation circuit comprises an inverting amplifier comprising an input terminal and output terminal which are coupled, respectively, to an output side and an input side of the crystal oscillator, a voltage at the output terminal comprising the oscillation signal. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the clock generating unit further comprises a trimming controller which generates a control signal for adjusting a gain of the inverting amplifier so that the effective value measured by the effective value measuring circuit will be equal to a target voltage. 
     
     
         6 . The semiconductor device according to  claim 5 , wherein the control signal comprises a 3-bit control signal, such that the gain of the inverting amplifier will be any one of eight gain values multiplied by a factor of 1 through 8. 
     
     
         7 . The semiconductor device according to  claim 5 , wherein the inverting amplifier comprises a plurality of switches which are configured with a transistor, and which are coupled between power supply and GND nodes of the inverting amplifier. 
     
     
         8 . The semiconductor device according to  claim 7 , wherein the switches are controlled by the control signal. 
     
     
         9 . The semiconductor device of  claim 5 , wherein the clock generating unit further comprises a comparison circuit comparing the effective value measured by the effective value measuring circuit to a reference voltage. 
     
     
         10 . The semiconductor device according to  claim 9 , wherein the effective value measuring circuit comprises:
 a differential pair to which respective voltages at the input terminal and at the output terminal of the inverting amplifier are input, respectively;   a constant current source supplying operating current to the differential pair; and   a low-pass filter coupled to an output node of the differential pair, an output of the low-pass filter being output to the comparison circuit, and the comparison circuit comparing the output of the low-pass filter to the reference voltage.   
     
     
         11 . The semiconductor device according to  claim 10 , wherein the comparison circuit obtains a difference value between the effective value and the reference voltage as a result of the comparison. 
     
     
         12 . The semiconductor device according to  claim 11 , wherein the clock generating unit further comprises an A/D converter which makes an A/D conversion of the difference value from the comparison circuit to generate a digital difference value, and
 wherein the trimming controller compares the digital difference value and a target digital difference value to generate the control signal.   
     
     
         13 . The semiconductor device according to  claim 12 , wherein the clock generating circuit further comprises a register for storing a target difference value,
 wherein before an adjustment is made by the trimming controller, the target difference value is set into the register, and   wherein after the target difference value is set into the register, the digital difference value is input to the trimming controller, and the trimming controller compares the digital difference value to the target difference value set in the register.   
     
     
         14 . The semiconductor device according to  claim 13 , wherein If a mismatch occurs between the digital difference value and the target difference value, then the trimming controller determines that a driving power of the oscillation circuit is not optimal and decrements the control signal to adjust the gain of the inverting amplifier, and
 after the trimming controller adjusts the gain of the inverting amplifier, the A/D converter generates a new digital difference value, and the trimming controller compares the new digital difference value to the target difference value.   
     
     
         15 . The semiconductor device according to  claim 14 , wherein the clock generating unit repeats the adjusting of the gain of the inverting amplifier by the trimming controller, the generating of a new digital difference value by the A/D converter, and the comparing of the new digital difference value to the target difference value by the trimming controller, until a match occurs between the digital difference value and the target difference value.