Dc-dc converter and control method for the same

Abstract

A DC-DC converter according to the present invention includes a power supply control circuit—that generates pulse signals, an output transistor that is controlled to be turned on and off based on the pulse signal, a rectification transistor—that is controlled to be turned on and off based on a control signal, a coil provided between a node between the output transistor and the rectification transistor, and an external output terminal, a comparator that compares a voltage of the node—with a reference voltage, a first control circuit that generates a control signal based on a comparison result of the comparator, and a second control circuit that generates the control signal based on a backward-current detection timing and a reference timing.

What is claimed is: 
     
         1 . A circuit for a DC-DC converter comprising:
 an input voltage terminal to which an input voltage is to be supplied;   an output node to which an inductor is to be coupled;   a reference voltage terminal to which a reference voltage is to be supplied;   a power supply control circuit that generates first and second pulse signals of a predetermined duty ratio;   a P-channel MOSFET having a source-drain path coupled between the input voltage terminal and the output node, and a gate coupled to receive the first pulse signal;   an N-channel MOSFET having a source-drain path coupled between the output node and the reference voltage terminal, and a gate coupled to receive a second control signal;   a comparison circuit having a first input coupled to the output node, a second input coupled to the reference voltage, and an output for outputting a comparison result;   a first control circuit that outputs, as a first control signal, one of the second pulse signal that turns on and off the N-channel MOSFET complementarily with the P-channel MOSFET and a first mask signal that turns off the N-channel MOSFET, based on the comparison result; and   a second control circuit that
 outputs, when a detection timing is later than a reference timing in a given cycle, the first control signal as the second control signal during a next cycle, and 
 outputs, when the detection timing is the same as or earlier than the reference timing in a given cycle, a second mask signal as the second control signal during a next cycle, the detection timing being a timing at which it has been determined by the comparison result that a current is flowing backward toward the N-channel MOSFET from the output node, the second mask signal being used to turn off the N-channel MOSFET. 
   
     
     
         2 . The circuit according to  claim 1 ,
 wherein the first control circuit includes:   a first flip-flop that generates the first mask signal based on the comparison result and the second pulse signal; and   a first AND circuit that outputs AND of the second pulse signal and the first mask signal as the first control signal.   
     
     
         3 . The circuit according to  claim 1 ,
 wherein the second control circuit includes:   a low load control circuit that generates the second mask signal based on the detection timing and the reference timing; and   a second AND circuit that outputs AND of the first control signal and the second mask signal as the second control signal.   
     
     
         4 . The circuit according to  claim 3 ,
 wherein the low load control circuit has:   a second flip-flop that generates an intermediate signal of a predetermined logical value according to a logical value of the comparison result having changed to a logical value indicating a current backflow, and initializes the intermediate signal according to a logical value of the second pulse signal having changed to a logical value to turn off the N-channel MOSFET; and   a third flip-flop that takes in a delay signal in which a predetermined delay has been added to the intermediate signal in synchronization with the intermediate signal, and outputs it as the second mask signal.   
     
     
         5 . The circuit according to  claim 3 ,
 wherein the low load control circuit has:   a second flip-flop that generates an intermediate signal of a predetermined logical value according to a logical value of the comparison result having changed to a logical value indicating a current backflow, and initializes the intermediate signal according to a logical value of the second pulse signal having changed to a logical value to turn off the second switching element;   a pulse generation circuit that generates a third pulse signal with a cycle according to the second pulse signal; and   a third flip-flop that takes in the intermediate signal in synchronization with the third pulse signal, and outputs it as the second mask signal.   
     
     
         6 . The circuit according to  claim 1 ,
 wherein the reference timing is decided based on a timing of logical value change of the second pulse signal.