Semiconductor memory device and production method thereof

Abstract

A semiconductor memory device according to an embodiment has a memory cell array including: a plurality of lower wirings extending in the first direction; a plurality of upper wirings extending in the second direction, the upper wirings placed above the plurality of lower wirings; a plurality of memory cells provided at respective crossings of the plurality of lower wirings and the plurality of upper wirings; and an interlayer insulating film provided between the plurality of memory cells adjacent in the second direction, and the device is characterized in that the upper wiring includes: an upper firing first section deposited on the memory cell; and an upper wiring second section deposited on the interlayer insulating film, the upper wiring second section larger in crystal grain size than the upper wiring first section, and an upper surface of the memory cell is lower than an upper surface of the interlayer insulating film.

What is claimed is: 
     
         1 . A method for producing a semiconductor memory device, the method comprising:
 when two directions crossing one another are referred to as a first direction and a second direction, whereas a direction crossing the first direction and the second direction is referred to as a vertical direction,   forming a stacked body having a lower wiring layer formed on a semiconductor substrate, a memory cell layer formed on the lower wiring layer, and a plurality of interlayer insulating film dividing, in the first direction, the lower wiring layer and the memory cell layer into more than one section and extending in the second direction;   removing an upper portion of the memory cell so that an upper surface of the memory cell layer is lower than an upper surface of the interlayer insulating film; and   stacking an upper wiring layer on the memory cell layer and the interlayer insulating film.   
     
     
         2 . The production method of a semiconductor memory device according to  claim 1 ,
 wherein a dry etching method is used in removing an upper portion of the memory cell layer.   
     
     
         3 . The production method of a semiconductor memory device according to  claim 1 ,
 wherein a wet etching method is used in removing an upper portion of the memory cell layer.   
     
     
         4 . The production method of a semiconductor memory device according to  claim 1 ,
 wherein CMP (Chemical Mechanical Polishing) is used in removing an upper portion of the memory cell layer.   
     
     
         5 . The production method of a semiconductor memory device according to  claim 1 ,
 wherein an ashing method is used to alter an upper portion of the memory cell layer, before removing an upper portion of the memory cell layer.   
     
     
         6 . The production method of a semiconductor memory device according to  claim 1 ,
 wherein an upper electrode layer in contact with the upper wiring layer is stacked as a portion of the memory cell layer in forming the stacked body.   
     
     
         7 . The production method of a semiconductor memory device according to  claim 6 ,
 wherein the upper electrode comprises titanium nitride (TiN),   the interlayer insulating film comprises a silicon oxide (SiO 2 ), and   the upper wiring comprises tungsten (W).   
     
     
         8 . The production method of a semiconductor memory device according to  claim 1 ,
 wherein the upper wiring layer is stacked so that a growth rate on the interlayer insulating film is quicker than a growth rate on the memory cell layer, in stacking the upper wiring layer.   
     
     
         9 . The production method of a semiconductor memory device according to  claim 1 ,
 wherein in forming the stacked body,   the lower wiring layer is stacked on the semiconductor substrate,   the memory cell layer is stacked on the lower wiring layer,   a plurality of first grooves extending in the first direction is formed in the memory cell layer and the lower wiring layer, and   the first grooves are filled with the interlayer insulating film.