Semiconductor device including zener diode and method of manufacturing thereof

Abstract

An embodiment of the present disclosure provides a semiconductor device. The semiconductor device includes an insulator formed on a top surface of a semiconductor substrate. The semiconductor device also includes a semiconductor layer containing a first region of a first conductivity type and formed on the insulator layer. The first region is a P+ region or an N+ region and has a volume of over 50-80% of that of the semiconductor layer. The semiconductor device further includes a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region. The second region has a doping concentration heavier than that of the first region. In addition, the semiconductor device includes a first metallization region in electrical contact with the first region and a second metallization region in electrical contact with the second region.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 an insulator formed on a top surface of a semiconductor substrate;   a semiconductor layer, containing a first region of a first conductivity type, formed on the insulator layer, wherein the first region is a P+ region or an N+ region and has a volume of over 50-80% of the volume of the semiconductor layer;   a second region of a second conductivity type in direct contact with the first region and forming a P-N junction with the first region;   a first metallization region in electrical contact with the first region; and   a second metallization region in electrical contact with the second region.   
     
     
         2 . The semiconductor device as claimed in  claim 1 , wherein the second region is formed in the semiconductor layer and is surrounded by the first region. 
     
     
         3 . The semiconductor device as claimed in  claim 2 , wherein the semiconductor layer does not include a third region other than the first region and the second region. 
     
     
         4 . The semiconductor device as claimed in  claim 2 , wherein the semiconductor layer is electrically and physically isolated with the semiconductor substrate by the insulator. 
     
     
         5 . The semiconductor device as claimed in  claim 1 , wherein the second region is the semiconductor substrate and partially covered by the semiconductor layer. 
     
     
         6 . The semiconductor device as claimed in  claim 5 , wherein semiconductor layer has an extension portion extending over a sidewall of the insulator and in direct contact with the semiconductor substrate. 
     
     
         7 . The semiconductor device as claimed in  claim 5 , wherein second metallization contact is physical contact with a portion of the second region that is not covered by the semiconductor layer. 
     
     
         8 . The semiconductor device as claimed in  claim 7 , wherein the second metallization contact has a horizontal gap with the semiconductor layer. 
     
     
         9 . The semiconductor device as claimed in  claim 1 , wherein the semiconductor layer comprises silicon. 
     
     
         10 . The semiconductor device as claimed in  claim 1 , wherein the semiconductor layer comprises GaN, GaAs or other III-V semiconductor materials. 
     
     
         11 . The semiconductor device as claimed in  claim 1 , wherein the insulator comprises a local oxidation of silicon structure. 
     
     
         12 . The semiconductor device as claimed in  claim 1 , wherein the insulator comprises a shallow trench isolation structure. 
     
     
         13 . A method for manufacturing a semiconductor device, comprising:
 forming an insulator on a semiconductor substrate;   depositing a semiconductor layer over the insulator and the semiconductor substrate;   performing a first implantation process on the semiconductor layer to give it a first conductivity type;   patterning the semiconductor layer such that the semiconductor layer is isolated with the semiconductor substrate by the insulator;   forming a photoresist layer over the semiconductor substrate, wherein the photoresist layer has an opening exposing a portion of the semiconductor layer; and   performing a second implantation process on the exposed portion of the semiconductor layer, through the opening, to form a region of a second conductivity type in the semiconductor layer.   
     
     
         14 . The method as claimed in  claim 13 , further comprising:
 removing the photoresist layer after performing the second implantation process;   forming an inter-layer dielectric layer over the semiconductor substrate;   forming a first metallization contact and a second metallization contact in electrical contact with the remaining region of the semiconductor layer that has the first conductivity type and the region of the second conductivity type, respectively.   
     
     
         15 . The method as claimed in  claim 13 , wherein the semiconductor layer is entirely implanted without using a mask in the first implantation process. 
     
     
         16 . A method for manufacturing a semiconductor device, comprising:
 forming an insulator on a semiconductor substrate;   depositing a semiconductor layer over the insulator and the semiconductor substrate;   performing a first implantation process on the semiconductor layer to give it a first conductivity type;   patterning the semiconductor layer such that the semiconductor layer is partially located on the insulator and has an extension portion in direct contact with the semiconductor substrate;   forming a photoresist layer over the semiconductor substrate, wherein the photoresist layer has an opening exposing a portion of extension portion of the semiconductor layer and a portion of the semiconductor substrate; and   performing a second implantation process on the semiconductor substrate, through the opening, to form a region of a second conductivity type in the semiconductor substrate, wherein the region of the second conductivity type is partially covered by the semiconductor layer.   
     
     
         17 . The method as claimed in  claim 16 , further comprising:
 removing the photoresist layer after performing the second implantation process;   forming an inter-layer dielectric layer over the semiconductor substrate and the semiconductor layer;   forming a first metallization contact and a second metallization contact in electrical contact with the semiconductor layer of the first conductivity type and the region of the second conductivity type, respectively.   
     
     
         18 . The method as claimed in  claim 16 , wherein the second implantation process uses an ion energy ranging from about 5 KeV to about 250 KeV. 
     
     
         19 . The method as claimed in  claim 16 , wherein the semiconductor layer is entirely implanted without using a mask in the first implantation process. 
     
     
         20 . The method as claimed in  claim 16 , wherein the opening of the photoresist layer comprises exposing a sidewall of the semiconductor layer.