Device including a floating gate electrode and a layer of ferroelectric material and method for the formation thereof

Abstract

An illustrative device disclosed herein includes a semiconductor substrate. The substrate includes a source region, a drain region and a channel region. The channel region is arranged between the source region and the drain region. A gate insulation layer is provided over the channel region. A floating gate electrode is provided over the gate insulation layer. A layer of a ferroelectric material is provided over the floating gate electrode. A top electrode is provided over the layer of ferroelectric material. A projected area of the top electrode onto a plane that is perpendicular to a thickness direction of the semiconductor substrate is smaller than a projected area of the floating gate electrode onto the plane.

1 . A device, comprising:
 a semiconductor substrate comprising a source region, a drain region and a channel region, said channel region being arranged between said source region and said drain region;   a gate insulation layer provided over said channel region;   a floating gate electrode provided over said gate insulation layer;   a layer of a ferroelectric material provided over said floating gate electrode, said layer of ferroelectric material defining a recess; and   a top electrode disposed in said recess, wherein a top surface of said top electrode does not extend beyond said recess;   wherein a projected area of said top electrode onto a plane that is perpendicular to a thickness direction of said semiconductor substrate is smaller than a projected area of said floating gate electrode onto said plane.   
     
     
         2 . The device of  claim 1 , wherein said layer of ferroelectric material comprises an oxide comprising at least one of hafnium and zirconium. 
     
     
         3 . The device of  claim 2 , wherein said top electrode comprises titanium nitride. 
     
     
         4 . The device of  claim 3 , wherein an extension of said top electrode in a channel length direction from said source region to said drain region is smaller than an extension of said floating gate electrode in said channel length direction. 
     
     
         5 . The device of  claim 4 , wherein an extension of said top electrode in a channel width direction that is perpendicular to said thickness direction of said semiconductor substrate and said channel length direction is smaller than an extension of said floating gate electrode in said channel width direction. 
     
     
         6 . The device of  claim 5 , wherein said layer of ferroelectric material comprises hafnium dioxide. 
     
     
         7 . The device of  claim 6 , wherein said floating gate electrode comprises at least one of tantalum nitride, titanium nitride and polysilicon. 
     
     
         8 . The device of  claim 7 , wherein said gate insulation layer includes a material having a greater dielectric constant than silicon dioxide. 
     
     
         9 . (canceled) 
     
     
         10 . The device of  claim 1 , further comprising a sidewall spacer adjacent and covering vertical surfaces of said floating gate electrode and said layer of ferroelectric material, said layer of ferroelectric material covering vertical surfaces of said top electrode and exposing a top surface of said top electrode. 
     
     
         11 - 28 . (canceled) 
     
     
         29 . A device, comprising:
 a semiconductor substrate comprising a source region, a drain region and a channel region, said channel region being arranged between said source region and said drain region;   a gate insulation layer provided over said channel region;   a floating gate electrode provided over said gate insulation layer;   a layer of a ferroelectric material provided over said floating gate electrode, said layer of ferroelectric material defining a recess; and   a top electrode disposed in said recess, wherein a top surface of said top electrode does not extend beyond said recess, wherein:   an extension of said top electrode in a channel length direction from said source region to said drain region is smaller than an extension of said floating gate electrode in said channel length direction;   an extension of said top electrode in a channel width direction that is perpendicular to a thickness direction of said semiconductor substrate and said channel length direction is smaller than an extension of said floating gate electrode in said channel width direction; and   a projected area of said top electrode onto a plane that is perpendicular to said thickness direction of said semiconductor substrate is smaller than a projected area of said floating gate electrode onto said plane.   
     
     
         30 . The device of  claim 29 , wherein said layer of ferroelectric material comprises an oxide comprising at least one of hafnium and zirconium. 
     
     
         31 . The device of  claim 29 , wherein said top electrode comprises titanium nitride. 
     
     
         32 . The device of  claim 31 , wherein said layer of ferroelectric material comprises hafnium dioxide. 
     
     
         33 . The device of  claim 32 , wherein said floating gate electrode comprises at least one of tantalum nitride, titanium nitride and polysilicon. 
     
     
         34 . The device of  claim 29 , wherein said gate insulation layer includes a material having a greater dielectric constant than silicon dioxide. 
     
     
         35 . (canceled) 
     
     
         36 . The device of  claim 29 , further comprising a sidewall spacer adjacent and covering vertical surfaces of said floating gate electrode and said layer of ferroelectric material, said layer of ferroelectric material covering vertical surfaces of said top electrode. 
     
     
         37 . A device, comprising:
 a semiconductor substrate comprising a source region, a drain region and a channel region, said channel region being arranged between said source region and said drain region;   a gate insulation layer provided over said channel region;   a floating gate electrode provided over said gate insulation layer;   a layer of a ferroelectric material provided over said floating gate electrodes, said layer of ferroelectric material defining a recess; and   a top electrode disposed in said recess, wherein a top surface of said top electrode does not extend beyond said recess.   
     
     
         38 . The device of  claim 37 , wherein an extension of said top electrode in a channel length direction from said source region to said drain region is smaller than an extension of said floating gate electrode in said channel length direction. 
     
     
         39 . The device of  claim 38 , wherein an extension of said top electrode in a channel width direction that is perpendicular to said thickness direction of said semiconductor substrate and said channel length direction is smaller than an extension of said floating gate electrode in said channel width direction. 
     
     
         40 . The device of  claim 37 , wherein said gate insulation layer includes a material having a greater dielectric constant than silicon dioxide. 
     
     
         41 . The device of  claim 37 , further comprising a sidewall spacer adjacent and covering vertical surfaces of said floating gate electrode and said layer of ferroelectric material, said layer of ferroelectric material covering vertical surfaces of said top electrode.