Bulk and dielectric-isolated finfet-based integrated circuit

Abstract

A method for forming a dielectric-isolated bulk fin field-effect transistor (finFET) device includes forming a second isolation layer over a first structure including multiple partially exposed fins and horizontal areas including a first isolation layer. The second isolation layer is removed from horizontal areas of a first portion of the first structure. An oxide layer is formed under the fins of the first portion of the first structure. The second isolation layer is removed in order to expose the partially exposed fins and horizontal areas of the first structure to form a second structure, on which gate regions are formed.

What is claimed is: 
     
         1 . A fin field-effect transistor (finFET) circuit, the finFET circuit comprising:
 a substrate;   a plurality of bulk finFET devices formed on the substrate; and   a plurality of dielectric-isolated bulk finFET devices, at least some of the dielectric-isolated bulk finFET devices including a fin that is isolated from the substrate by an oxide layer formed under an active portion of the fin, wherein the active portion of the fin is above a first isolation layer.   
     
     
         2 . The finFET circuit of  claim 1 , further comprising a second isolation layer comprising a silicon nitride layer formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). 
     
     
         3 . The finFET circuit of  claim 2 , wherein the second isolation layer covers active portions of fins of the plurality of bulk finFET devices and the plurality of dielectric-isolated bulk finFET devices. 
     
     
         4 . The finFET circuit of  claim 1 , wherein the substrate comprises silicon, and wherein the first isolation layer comprises a shallow-trench isolation (STI) layer. 
     
     
         5 . The finFET circuit of  claim 1 , wherein oxide layers under active portions of fins of the plurality of dielectric-isolated bulk finFET devices are formed by an oxidation process, for which the first isolation layer is not a barrier. 
     
     
         6 . The finFET circuit of  claim 1 , further comprising gate regions formed over active portions of fins of the plurality of bulk finFET devices and the plurality of dielectric-isolated bulk finFET devices. 
     
     
         7 . The finFET circuit of  claim 6 , wherein the gate regions comprise a gate oxide layer, a high-K dielectric layer, and a work-function metal and gate metal layer. 
     
     
         8 . The finFET circuit of  claim 1 , wherein the plurality of bulk finFET devices are employed to implement vertical bipolar-junction transistors, laterally-diffused MOS (LDMOS) devices, electrostatic discharge (ESD) diodes, or varactor devices using fin-FET-based CMOS technology. 
     
     
         9 . The finFET circuit of  claim 1 , wherein the plurality of dielectric-isolated bulk finFET devices are employed to implement fin-FET-based CMOS technology integrated circuits including memory and logic circuitry using. 
     
     
         10 . The finFET circuit of  claim 1 , wherein the plurality of bulk finFET devices and the plurality of dielectric-isolated bulk finFET devices are formed concurrently by employing fin-FET-based CMOS technology. 
     
     
         11 . A communication device, comprising:
 analog circuitry formed on a substrate; and   digital circuitry formed on the substrate,   wherein the analog circuitry comprises a plurality of bulk finFET devices, and wherein the digital circuitry comprises a plurality of dielectric-isolated bulk finFET devices, at least some of the dielectric-isolated bulk finFET devices including a fin that is isolated from the substrate by an oxide layer formed under an active portion of the fin, wherein the active portion of the fin is above a first isolation layer.   
     
     
         12 . The communication device of  claim 11 , wherein the plurality of bulk finFET devices and the plurality of dielectric-isolated bulk finFET devices comprise a second isolation layer comprising a silicon nitride layer formed by atomic-layer deposition (ALD) or molecular-layer deposition (MLD). 
     
     
         13 . The communication device of  claim 12 , wherein the second isolation layer covers active portions of fins of the plurality of bulk finFET devices and the plurality of dielectric-isolated bulk finFET devices. 
     
     
         14 . The communication device of  claim 11 , wherein the substrate comprises silicon, and wherein the first isolation layer comprises a shallow-trench isolation (STI) layer. 
     
     
         15 . The communication device of  claim 11 , wherein oxide layers under active portions of fins of the plurality of dielectric-isolated bulk finFET devices are formed by an oxidation process, for which the first isolation layer is not a barrier. 
     
     
         16 . The communication device of  claim 11 , wherein the plurality of bulk finFET devices and the plurality of dielectric-isolated bulk finFET devices further comprise gate regions formed over active portions of fins of the plurality of bulk finFET devices and the plurality of dielectric-isolated bulk finFET devices. 
     
     
         17 . The communication device of  claim 16 , wherein the gate regions comprise a gate oxide layer, a high-K dielectric layer, and a work-function metal and gate metal layer. 
     
     
         18 . The communication device of  claim 11 , wherein the analog circuitry comprises at least one of vertical bipolar junctiontransistors, laterally-diffused MOS (LDMOS) devices, electrostatic discharge (ESD) diodes, or varactor devices using fin-FET-based CMOS technology. 
     
     
         19 . An integrated circuit comprising:
 a plurality of bulk finFET devices formed on a substrate; and   a plurality of dielectric-isolated bulk finFET devices, at least some of the dielectric-isolated bulk finFET devices including a fin that is isolated from the substrate by an oxide layer, wherein the oxide layer is formed under an active portion of the fin, wherein the active portion of the fin is covered by a gate structure.   
     
     
         20 . The integrated circuit of  claim 19 , wherein the gate structure comprises a gate oxide layer, a high-K dielectric layer, and a work-function metal and gate metal layer.