Structure and method to minimize warpage of packaged semiconductor devices

Abstract

A packaged semiconductor device includes a substrate, an electronic device coupled to the substrate, encapsulant including a first major surface surrounding the electronic device, and an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant. The oxygen barrier covers at least a portion of an area of the second major surface of the encapsulant to help reduce or eliminate warping of the encapsulant and/or the substrate of the packaged semiconductor device due to oxidation. A thickness of the oxygen barrier layer is less than 100 microns.

1 . A packaged semiconductor device, comprising:
 a substrate;   an electronic device coupled to the substrate;   encapsulant including a first major surface surrounding the electronic device; and   an oxygen barrier layer within fifty percent of a thickness of the encapsulant from a second major surface of the encapsulant, the oxygen barrier covering at least a portion of an area of the second major surface of the encapsulant, wherein a thickness of the oxygen barrier layer is less than 100 microns.   
     
     
         2 . The device of  claim 1 , wherein the oxygen barrier is in direct contact with the second major surface of the encapsulant. 
     
     
         3 . The device of  claim 1 , wherein the thickness of the oxygen barrier layer is greater than 1 nanometer. 
     
     
         4 . The device of  claim 1 , further comprising the oxygen barrier layer covers at least one sidewall of the encapsulant. 
     
     
         5 . The device of  claim 1 , further comprising the oxygen barrier layer covers at least a portion of a major surface of the substrate. 
     
     
         6 - 7 . (canceled) 
     
     
         8 . The device of  claim 1 , wherein the oxygen barrier layer includes a first layer of a first material and a second layer of a second material. 
     
     
         9 - 13 . (canceled) 
     
     
         14 . A packaged semiconductor device, comprising:
 a substrate having a top surface;   a semiconductor die coupled to the top surface of the substrate;   encapsulant surrounding the semiconductor die and covering at least a portion of the top surface of the substrate, the encapsulant having a first major surface in contact with the top surface of the substrate, and a second major surface opposing the first major surface; and   oxygen barrier material covering at least a portion of the second major surface of the encapsulant, wherein a thickness of the oxygen barrier material is less than 100 microns, and the oxygen barrier material is configured to reduce diffusion of oxygen from an ambient environment to the encapsulant.   
     
     
         15 . The device of  claim 14 , wherein the oxygen barrier material is in direct contact with the second major surface of the encapsulant. 
     
     
         16 . The device of  claim 14 , wherein the thickness of the oxygen barrier material is greater than 1 nanometer. 
     
     
         17 . The device of  claim 14 , further comprising the oxygen barrier material covers at least one sidewall of the encapsulant. 
     
     
         18 . The device of  claim 14 , further comprising the oxygen barrier material covers at least a portion of a bottom surface of the substrate, the bottom surface opposing the top surface of the substrate. 
     
     
         19 . The device of  claim 14 , wherein the oxygen barrier material includes a first layer of a first material and a second layer of a second material. 
     
     
         20 . The device of  claim 14 , wherein a form factor of the packaged semiconductor device is one of a group consisting of: a through-hole, surface mount, chip carrier, pin grid array, flat package, small outline package, chip-scale package, redistributed chip package, wafer level fan-out, and ball grid array. 
     
     
         21 . The device of  claim 14 , wherein the oxygen barrier material includes at least one of a group comprising: ceramic coating, ceramic oxide coating, zirconium oxide coating, alumina coating, synthetic rubber based coating, butyl rubber with filler, nitrile rubber with filler, polyurethane based coating, silicone based coating, silsesquioxane based coatings, and polymeric material with or without filler. 
     
     
         22 . The device of  claim 14 , wherein the oxygen barrier material is applied by at least one of a group comprising: atomic layer deposition, physical vapor deposition, chemical vapor deposition, electrochemical deposition, sol-gel deposition, self-aligned monolayer coating, melting and enameling process, spin coating, spray coat, rolling on, brushing on, sponging on, dip coating. 
     
     
         23 . The device of  claim 14 , further comprising a plurality of connections attached to a bottom surface of the substrate, the bottom surface opposing the top surface of the substrate. 
     
     
         24 . The device of  claim 14 , further comprising a plurality of wire bonds attached to the semiconductor die and the top surface of the substrate, the plurality of wire bonds surrounded by the encapsulant. 
     
     
         25 . The device of  claim 14 , wherein a thickness of the encapsulant is 500 microns or less. 
     
     
         26 . The device of  claim 14 , wherein a warpage of the packaged semiconductor device is within a range of 20 to 100 microns. 
     
     
         27 . The device of  claim 14 , wherein the oxygen barrier material is thermally stable and has good adhesion to materials utilized in the packaged semiconductor device.