Multi-level ladder dac with dual-switch interconnect to ladder nodes

Abstract

A multi-level DAC includes first and second level resistor ladders, and a dual-switch ladder interconnect reduces DNL at tap-point transitions between first-level ladder resistors. For each first level resistor N, the switch-interconnect network includes dual (first/second) switches connectable to a resistor-top node NT, and dual (third/fourth) switches selectively connectable to a resistor-bottom node NB. The first switch is operable to connect NT to a top tap switch operable to select NT as a top tap point, and the fourth interconnect switch is operable to connect NB to a bottom tap switch operable to select NB as a bottom tap point. The first and fourth switches are connected, forming an outer loop that includes top and bottom tap points. The second switch connects to a top second-level resistor RT, and the third switch connects to a bottom second-level resistor RB, forming an inner loop that includes the series-connected second-level resistors.

1 . A DAC (digital to analog converter) circuit, comprising
 a first-first level resistor ladder including multiple series-connected resistors, including a resistor N connected to a previous resistor N−1 at a respective top ladder node NT, and to a next resistor N+1 at a respective bottom ladder node NB;   a second-level resistor ladder including multiple series-connected resistors, starting with a top resistor RT and ending with a bottom resistor RB, and with tap nodes between each second-level resistor, each tap node connected to a tap switch operable to select the tap node as a respective tap point; and   a switch-interconnect network configured to selectively connect the second-level ladder across each first-level resistor N at the NT and NB ladder nodes, including
 dual (first and second) interconnect switches selectively connectable to the NT ladder node; and 
 dual (third and fourth) interconnect switches selectively connectable to the NB ladder node; 
 such that,
 the first interconnect switch is operable to connect the NT node to a top tap switch operable to select the NT node as a top tap point, and 
 the fourth interconnect switch is operable to connect the NB node to a bottom tap switch operable to select the NB node as a bottom tap point, 
 the first and fourth switches are connected, forming an outer loop that includes the top tap point and the bottom tap point; and 
 
 such that
 the second interconnect switch connects to RT, and 
 the third interconnect switch connects to RB, 
 forming an inner loop that includes the series-connected second-level resistors. 
 
   
     
     
         2 . The circuit of  claim 1 , wherein
 the top second-level resistor RT is sized such that the resistance value of RT plus the resistance of the second interconnect switch is equal to a target resistance; and   the bottom second-level resistor RB is sized such that the resistance value of RB plus the resistance of the third interconnect switch is equal to a target resistance.