Clock generation circuit, display device drive circuit, and control method of clock generation circuit

Abstract

A clock generation circuit that can reliably recover from a state in which generation of a clock is stopped even during a power-on process and a normal operation. The clock generation circuit includes a clock extraction circuit that extracts an extracted clock from an embedded signal on which a clock and data are superimposed, and a stop detection circuit that detects a stop of the extracted clock on the basis of the embedded signal and the extracted clock and outputs a reset signal that resets the clock extraction circuit to an initial state.

What is claimed is: 
     
         1 . A serial I/F circuit comprising:
 a receiving circuit outputs an embedded signal on which a clock and serial data are superimposed and outputs an embedded signal;   a clock extraction circuit that extracts an extracted clock from the embedded signal;   a serial-parallel conversion circuit that converts the embedded signal into parallel data on the basis of the recovery clock; and   a stop detection circuit that detects a stop of the extracted clock on the basis of the embedded signal and the extracted clock and outputs a reset signal that resets the clock extraction circuit to an initial state.   
     
     
         2 . The serial I/F circuit according to  claim 1 , wherein the stop detection circuit outputs the reset signal when the extracted clock is not detected while the embedded signal is detected. 
     
     
         3 . The serial I/F circuit to  claim 1 ,
 wherein the stop detection circuit includes:
 an embedded signal monitoring unit that generates a first comparison signal based on the embedded signal, 
 an extracted clock monitoring unit that generates a second comparison signal based on the extracted clock, and 
 a comparator that compares the first comparison signal with the second comparison signal and outputs the reset signal based on a result of the comparison. 
   
     
     
         4 . The serial I/F circuit to  claim 3 ,
 wherein the embedded signal monitoring unit is a frequency dividing circuit that divides a frequency of the embedded signal, and   wherein the first comparison signal is a frequency-divided signal obtained by dividing a frequency of the embedded signal.   
     
     
         5 . The serial I/F circuit according to  claim 4 , wherein the data is a serial signal having a fixed data length and the frequency dividing circuit is a frequency dividing circuit that divides the frequency of the embedded signal by a number larger than the data length of the serial signal. 
     
     
         6 . The serial I/F circuit according to  claim 4 , wherein the frequency dividing circuit divides the frequency of the embedded signal so that a period of a frequency-divided signal is longer than a period of the extracted clock. 
     
     
         7 . The serial I/F circuit to  claim 3 , wherein the extracted clock monitoring unit generates the second comparison signal based on the extracted clock and the first comparison signal. 
     
     
         8 . The serial I/F circuit according to  claim 7 , wherein the extracted clock monitoring unit is a shift circuit that generates the second comparison signal obtained by shifting timing of the first comparison signal according to the extracted clock. 
     
     
         9 . The serial I/F circuit according to  claim 8 ,
 wherein the shift circuit includes a flip-flop, and   wherein the flip-flop latches the first comparison signal according to the extracted clock and outputs the latched signal as the second comparison signal.   
     
     
         10 . The serial I/F circuit according to  claim 3 , wherein when a signal level of the first comparison signal and a signal level of the second comparison signal do not correspond to each other, the comparator outputs the reset signal. 
     
     
         11 . The serial I/F circuit according to  claim 10 ,
 wherein the comparator includes an exclusive-OR circuit, and   wherein the exclusive-OR circuit performs an exclusive-OR operation on the first comparison signal and the second comparison signal and outputs a result of the operation as the reset signal.   
     
     
         12 . The serial I/F circuit according to  claim 3 , wherein while the extracted clock is outputted, the comparator compares the first comparison signal with the second comparison signal at timing when a high level period of the first comparison signal and a high level period of the second comparison signal overlap each other. 
     
     
         13 . The serial I/F circuit according to  claim 3 , wherein the comparator compares the first comparison signal with the second comparison signal at timing based on the embedded signal. 
     
     
         14 . The serial I/F circuit according to  claim 3 , wherein the comparator compares the first comparison signal with the second comparison signal at timing of a period shorter than a period of the first comparison signal. 
     
     
         15 . The serial I/F circuit according to  claim 3 ,
 wherein the first comparison signal is a frequency-divided signal obtained by dividing the frequency of the embedded signal by 2N (N is a natural number), and   wherein the comparator compares the first comparison signal with the second comparison signal at timing of a frequency-divided signal obtained by dividing the frequency of the embedded signal by 2N−1.   
     
     
         16 . The serial I/F circuit according to  claim 15 ,
 wherein the comparator includes a flip-flop, and   wherein the flip-flop latches a comparison result of the first comparison signal and the second comparison signal at timing of a frequency-divided signal obtained by dividing the frequency of the embedded signal by 2N−1 and outputs the latched signal as the reset signal.   
     
     
         17 . The serial I/F circuit according to  claim 1 , further comprising:
 a clock output circuit that outputs an extraction control signal that controls an extraction range of a clock,   wherein the clock extraction circuit extracts an extracted clock from the embedded signal on the basis of the extraction control signal.   
     
     
         18 . The serial I/F circuit according to  claim 1 , further comprising:
 a clock output circuit that is a delay locked loop circuit,   wherein the delay locked loop circuit includes a delay line circuit that generates a delay signal from the extracted clock, a phase comparator that generates a phase difference signal based on a phase difference between the delay signal and the extracted clock, and   a charge pump circuit that raises a voltage level of the phase difference signal and controls delay of the delay line circuit.