Integrated circuit

Abstract

According to one embodiment, provided are an amplifier transistor configured to amplify an input signal; a biasing circuit configured to set a bias voltage in such a manner as to allow the amplifier transistor to perform amplification; an electrostatic protective circuit configured to set the bias voltage for the amplifier transistor in such a manner as to make the amplifier transistor to turn off based on voltage to be applied to the amplifier transistor; and a switching circuit configured to switch the bias voltage for the amplifier transistor based on a power supply condition.

1 - 20 . (canceled) 
     
     
         21 . An integrated circuit, comprising:
 a first amplifier transistor including a gate and a source, the first amplifier configured to amplify an input signal;   a biasing circuit configured to supply a bias voltage to the gate of the first amplifier transistor;   an electrostatic protective circuit including a first resistance and a first switching transistor, wherein   the first resistance is electrically connected between a first power source and a gate of the first switching transistor, and   the first switching transistor is electrically connected between the gate and the source of the first amplifier transistor and configured to control the first amplifier transistor.   
     
     
         22 . The integrated circuit according to  claim 21 , wherein the first switching transistor is configured to input the bias voltage or a second power source to the gate of the first amplifier transistor. 
     
     
         23 . The integrated circuit according to  claim 21 , wherein the first resistance is connected between the first power supply and the gate of the first switching transistor via a first inverter and a second inverter. 
     
     
         24 . The integrated circuit according to  claim 23 , further comprising:
 an inductor connected to the source of the first amplifier transistor, and   a capacitor connected between the source and the gate of the amplifier transistor.   
     
     
         25 . The integrated circuit according to  claim 24 , further comprising:
 a second amplifier transistor connected in series to the first amplifier transistor.   
     
     
         26 . The integrated circuit according to  claim 25 , wherein a drain of the second amplifier transistor is electrically connected to the first power source via a diode, and the first power source is electrically connected to the second power source via a plurality of diodes. 
     
     
         27 . The integrated circuit according to  claim 26 , wherein a drain of the first switching transistor is electrically connected to the gate of the first amplifier transistor via a second resistance. 
     
     
         28 . The integrated circuit according to  claim 26 , wherein the first amplifier transistor, the second amplifier transistor, and the first switching transistor are n-channel field effect transistors. 
     
     
         29 . The integrated circuit according to  claim 21 , wherein
 the biasing circuit includes a first biasing transistor, a second biasing transistor, and a third biasing transistor;   a source of the first biasing transistor and a source of the second biasing transistor are connected to the first power source; and   a gate of the first biasing transistor, a drain of the first biasing transistor, and a gate of the second biasing transistor are connected in common; and wherein   the electrostatic protective circuit includes a first inverter, a second inverter, and a second switching transistor;   the first resistance is connected to an input of the first inverter;   an output of the first inverter is connected to an input of the second inverter;   an output of the second inverter is connected to the gate of the first switching transistor;   a source of the second switching transistor is connected to the first power source;   a drain of the second switching transistor is connected to the gate of the first biasing transistor; and   a gate of the second switching transistor is connected to the output of the first inverter.   
     
     
         30 . The integrated circuit according to  claim 29 , wherein a drain of the second biasing transistor, a drain of the third biasing transistor, a gate of the third biasing transistor, and a drain of the first switching transistor are connected in common, and the bias voltage is output from the drain of the second biasing transistor. 
     
     
         31 . The integrated circuit according to  claim 30 , further comprising:
 an inductor connected to the source of the first amplifier transistor, and   a capacitor connected between the source and the gate of the amplifier transistor.   
     
     
         32 . The integrated circuit according to  claim 31 , further comprising:
 a second amplifier transistor connected in series to the first amplifier transistor.   
     
     
         33 . The integrated circuit according to  claim 32 , wherein a drain of the second amplifier transistor is electrically connected to the first power source via a diode, and the first power source is electrically connected to the second power source via a plurality of diodes. 
     
     
         34 . The integrated circuit according to  claim 33 , wherein the drain of the first switching transistor is electrically connected to the gate of the first amplifier transistor via a second resistance. 
     
     
         35 . The integrated circuit according to  claim 34 , wherein
 the biasing circuit further includes a fourth biasing transistor, a fifth biasing transistor, and a sixth biasing transistor,   a source of the fourth biasing transistor is connected to the first power source;   a gate of the fourth biasing transistor is connected to the gate of the first biasing transistor;   a drain of the fourth biasing transistor, a drain of the fifth biasing transistor, and a gate of the fifth biasing transistor are connected in common;   a source of the fifth biasing transistor, a drain of the sixth biasing transistor, and a gate of the sixth biasing transistor are connected in common; and   a drain of the sixth biasing transistor is connected to a gate of the second amplifier transistor via a third resistance.   
     
     
         36 . The integrated circuit according to  claim 35 , wherein the first amplifier transistor, the second amplifier transistor, the first switching transistor, the third biasing transistor, the fifth biasing transistor, and the sixth biasing transistor are n-channel field effect transistors, and the second switching transistor, the first biasing transistor, the second biasing transistor, and the fourth biasing transistor are p-channel field effect transistors. 
     
     
         37 . An integrated circuit, comprising:
 a first amplifier transistor including a gate and a source, the first amplifier configured to amplify an input signal;   a second amplifier transistor including a gate and a source and connected in series to the first amplifier transistor;   a biasing circuit configured to supply a first bias voltage to the gate of the first amplifier transistor and supply a second bias voltage to the gate of the second amplifier transistor;   an electrostatic protective circuit including a first resistance and a first switching transistor, wherein   the first resistance is electrically connected between a first power source and a gate of the first switching transistor, and   the first switching transistor is electrically connected between the gate of the second amplifier transistor and a second power source, and configured to control the second amplifier transistor.   
     
     
         38 . The integrated circuit according to  claim 37 , wherein the first switching transistor is configured to input the second bias voltage or the second power source to the gate of the second amplifier transistor. 
     
     
         39 . The integrated circuit according to  claim 38 , wherein the first resistance is connected between the first power supply and the gate of the first switching transistor via a first inverter and a second inverter. 
     
     
         40 . The integrated circuit according to  claim 39 , wherein a drain of the second amplifier transistor is electrically connected to the first power source via a diode, and the first power source is electrically connected to the second power source via a plurality of diodes.