Three-dimensional semiconductor device

Abstract

A three-dimensional (3D) semiconductor device includes first interlayer dielectric layers and word lines that are alternately stacked on a substrate; select lines formed on the first interlayer dielectric layers and the word lines; etch stop patterns formed on the select lines to contact the select lines; channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines; channel layers formed on surfaces of the channel holes; insulating layers formed in the channel holes, the insulating layers having an upper surface that is lower than upper surfaces of the etch stop patterns; impurity-doped layers formed in channel holes on upper surface of the insulating layers; and a second interlayer dielectric layer formed over the etch stop patterns and the impurity-doped layers.

1 - 12 . (canceled) 
     
     
         13 . A semiconductor device, comprising:
 first interlayer dielectric layers and word lines that are alternately stacked on a substrate;   select lines formed on the first interlayer dielectric layers and the word lines;   etch stop patterns formed on the select lines to contact the select lines;   a pair of channel holes formed to pass through the select lines, the first interlayer dielectric layers, and the word lines;   a channel layer formed on a surface of the pair of channel holes;   an insulating layer formed in the pair of channel holes, the insulating layer having an upper surface that is lower than upper surfaces of the etch stop patterns;   impurity-doped layers formed in the pair of channel holes on the upper surface of the insulating layer; and   second interlayer dielectric layers formed over the etch stop patterns and the impurity-doped layers.   
     
     
         14 . The semiconductor device of  claim 13 , wherein bottom surfaces of the impurity-doped layers are formed to be higher than bottom surfaces of the select lines. 
     
     
         15 . The semiconductor device of  claim 13 , wherein the second interlayer dielectric layer is formed to be thicker than either one of the first interlayer dielectric layers, between the word lines, or each of the impurity-doped layers. 
     
     
         16 . The semiconductor device of  claim 13 , further comprising:
 a pipe gate formed under the first interlayer dielectric layers and the word lines; and   trenches formed in the pipe gate to connect the pair of channel holes; and where   the channel layer is formed on a surface of the trenches.   
     
     
         17 . The semiconductor device of  claim 13 , further comprising:
 a slit configured to pass through the select lines, the first interlayer dielectric layers, and the word lines.   
     
     
         18 . The semiconductor device of  claim 13 , wherein the first and second interlayer dielectric layers are oxide layers, and
 the etch stop patterns are nitride layers.   
     
     
         19 . A semiconductor device, comprising:
 first interlayer dielectric layers and word lines that are alternately stacked on a substrate;   a select line formed on the first interlayer dielectric layers and the word lines;   an etch stop pattern formed on the select line to contact the select line; and   a channel layer formed to pass through the select line, the etch stop pattern, the first interlayer dielectric layers, and the word lines.   
     
     
         20 . The semiconductor device of  claim 19 , further comprising:
 an insulating layer formed in the channel layer, the insulating layer having an upper surface that is lower than an upper surface of the etch stop pattern;   an impurity-doped layer formed in the channel layer and on the upper surface of the insulating layer; and   a second interlayer dielectric layer formed over the etch stop pattern and the impurity-doped layer.   
     
     
         21 . The semiconductor device of  claim 20 , wherein a bottom surface of the impurity-doped layer is formed to be higher than a bottom surface of the select line. 
     
     
         22 . The semiconductor device of  claim 20 , wherein the first and second interlayer dielectric layers are oxide layers, and
 the etch stop patterns is a nitride layer.