Three-dimensional semiconductor device and a system having the same

Abstract

A 3D semiconductor device and a system having the same are provided. The 3D semiconductor device includes a semiconductor substrate, a common source region formed on the semiconductor substrate and extending in a line shape, an active region formed on the common source region and including a lateral channel region, which is substantially in parallel to a surface of the semiconductor substrate, and source and drain regions that are branched from the lateral channel region to a direction substantially perpendicular to the surface of the semiconductor substrate, and a gate formed in a space between the source region and the drain region.

What is claimed is: 
     
         1 . A three-dimensional (3D) semiconductor device, comprising:
 a semiconductor substrate;   a common source region formed on the semiconductor substrate and extending in a line shape;   an active region formed on the common source region and including a lateral channel region, which is substantially in parallel to a surface of the semiconductor substrate, and source and drain regions that are branched from the lateral channel region to a direction substantially perpendicular to the surface of the semiconductor substrate;   a gate formed in a space between the source region and the drain region and extending substantially in parallel to the common source region;   heating electrodes formed on the source region and the drain region; and   resistance variable material layers formed on the heating electrodes,   wherein the resistance variable material layer on the drain region is electrically coupled to the heating electrode therebelow, and the resistance variable material layer on the source region is electrically isolated from the heating electrode therebelow.   
     
     
         2 . The 3D semiconductor device of  claim 1 , further comprising a gate insulating layer covered between the source region and the gate, between the drain region and the gate, between the lateral channel region and the gate, and between the semiconductor substrate and the gate. 
     
     
         3 . The 3D semiconductor device of  claim 1 , wherein the gate on the active region is located in a lower portion of a space between the source region and the drain region, and
 a gate protection layer is further formed on the gate.   
     
     
         4 . The 3D semiconductor device of  claim 1 , further comprising:
 a spacer formed on a sidewall of the resistance variable material layer on the drain region; and   a spacer insulating layer located on a sidewall of the resistance variable material layer on the source region, and between the resistance variable material layer on the source region and the heating electrode below the resistance variable material layer.   
     
     
         5 . The 3D semiconductor device of  claim 1 , wherein the active region is coupled to the common source region. 
     
     
         6 . The 3D semiconductor device of  claim 1 , wherein the common source region includes a semiconductor layer having different etch selectivity from that of each of semiconductor layers of the semiconductor substrate and the active region. 
     
     
         7 . The 3D semiconductor device of  claim 6 , wherein the semiconductor substrate and the active region include a silicon material, and the common source region includes a silicon germanium material. 
     
     
         8 . A microprocessor, comprising:
 a control unit suitable for receiving a signal including a command from the outside and performing extraction or decryption of the command, or input control or output control;   an operation unit suitable for performing an operation according to a decryption result of the command in the control unit; and   a storage unit suitable for storing one or more among data to be operated, data corresponding to a result of the operation, and an address for the data to be operated,   wherein the storage unit includes a transistor including a lateral channel formed on a line-shaped common source region, and a resistance variable material layer electrically coupled to the transistor.   
     
     
         9 . A processor, comprising:
 a core unit suitable for performing an operation corresponding to a command using a data according to a command input from the outside;   a cache semiconductor device unit suitable for storing one or more among data to be operated, data corresponding to a result of the operation, and an address for the data to be operated; and   a bus interface suitable for interconnecting the core unit and the cache semiconductor device unit, and transmitting data between the core unit and the cache semiconductor device unit,   wherein the cache semiconductor device unit includes a transistor including a lateral channel formed on a line-shaped common source region, and a resistance variable material layer electrically coupled to the transistor.   
     
     
         10 . A system, comprising:
 a processor suitable for interpreting a command input from the outside and controlling an operation of information according to an interpretation result of the command;   an auxiliary storage device suitable for storing a program for the interpretation of the command and the information;   a main storage device suitable for transferring the program and the information from the auxiliary storage unit and storing the program and the information so that the processor performs the operation using the program and the information when the program is executed; and   an interface device suitable for performing communication between the outside and one or more among the processor, the auxiliary storage device, and the main storage device,   wherein at least one of the auxiliary storage device and the main storage device includes a transistor including a lateral channel formed on a line-shaped common source region, and a resistance variable material layer electrically coupled to the transistor.