Semiconductor device with surrounding gate transistors in a nand circuit

Abstract

A semiconductor device employs surrounding gate transistors (SGTs) which are vertical transistors to constitute a CMOS NAND circuit. The NAND circuit is formed by using a plurality of MOS transistors arranged in m rows and n columns. The MOS transistors constituting the NAND circuit are formed on a planar silicon layer disposed on a substrate, and each have a structure in which a drain, a gate, and a source are arranged in a vertical direction, the gate surrounding a silicon pillar. The planar silicon layer includes a first active region having a first conductivity type and a second active region having a second conductivity type. The first active region and the second active region are connected to one another via a silicon layer formed on a surface of the planar silicon layer. This provides for a semiconductor device that constitutes a NAND circuit.

1 . A semiconductor device, comprising:
 a plurality of transistors arranged in two rows and n columns on a substrate, where n≧3, to constitute a NAND circuit, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate,   each of the plurality of transistors including:
 a silicon pillar, 
 an insulator surrounding a side surface of the silicon pillar, 
 a gate surrounding the insulator, 
 a source region disposed on an upper portion or a lower portion of the silicon pillar, and 
 a drain region disposed on an upper portion or a lower portion of the silicon pillar, the drain region being located on a side of the silicon pillar opposite to a side of the silicon pillar on which the source region is located, the plurality of transistors including: 
 n p-channel MOS transistors arranged in one row and n columns, and 
 n n-channel MOS transistors arranged in one row and n columns, 
   wherein the n p-channel MOS transistors and the n n-channel MOS transistors are arranged such that   a p-channel MOS transistor in a k-th column and an n-channel MOS transistor in the k-th column form a pair, where k=1 to n, the gate of the p-channel MOS transistor in the k-th column and the gate of the n-channel MOS transistor in the k-th column being connected to one another,   the drain regions of the n p-channel MOS transistors and the drain region of an n-channel MOS transistor in a first column are located on a side of the silicon pillars close to the substrate, the drain regions of the n p-channel MOS transistors and the drain region of the n-channel MOS transistor in the first column being connected to one another via a silicide region, and   the source region of an n-channel MOS transistor in an s-th column and the drain region of an n-channel MOS transistor in an (s+1)-th column are connected to one another, where s=1 to n−1.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein:
 the source regions of the n p-channel MOS transistors are connected to a power supply line extending along a row, and   the source region of an n-channel MOS transistor in an n-th column is connected to a reference power supply line extending along a row.   
     
     
         3 . The semiconductor device according to  claim 1 , wherein the n n-channel MOS transistors are arranged such that the source region of an n-channel MOS transistor in an even-numbered column is located on the side of the silicon pillar close to the substrate. 
     
     
         4 . The semiconductor device according to  claim 1 , wherein n input signals are connected to gates of n pairs of transistors whose gates are connected to one another so that each of the n input signals corresponds to gates of one of the n pairs of transistors. 
     
     
         5 . The semiconductor device according to  claim 4 , wherein:
 the source regions of the n n-channel MOS transistors are connected to a reference power supply line extending along a row, and   the source region of a p-channel MOS transistor in an n-th column is connected to a power supply line extending along a row,   each of the power supply line and the reference power supply line comprises a first metal line, and   each of the n input signals comprises a second metal line extending in a direction perpendicular to the power supply line and the reference power supply line.   
     
     
         6 . A semiconductor device, comprising:
 a plurality of transistors arranged in two rows and n columns on a substrate, where n≧4, to constitute a NAND circuit having g input signals, where n=h×g, and each of g and h is an integer, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate,   each of the plurality of transistors including:
 a silicon pillar, 
 an insulator surrounding a side surface of the silicon pillar, 
 a gate surrounding the insulator, 
 a source region disposed on an upper portion or a lower portion of the silicon pillar, and 
 a drain region disposed on an upper portion or a lower portion of the silicon pillar, the drain region being located on a side of the silicon pillar opposite to a side of the silicon pillar on which the source region is located, the plurality of transistors including: 
 n p-channel MOS transistors arranged in one row and n columns, and 
 n n-channel MOS transistors arranged in one row and n columns, 
   wherein the n p-channel MOS transistors and the n n-channel MOS transistors are arranged such that   a p-channel MOS transistor in a k-th column and an n-channel MOS transistor in the k-th column form a pair, where k=1 to n, the gate of the p-channel MOS transistor in the k-th column and the gate of the n-channel MOS transistor in the k-th column being connected to one another,   the drain regions of the n p-channel MOS transistors and the drain regions of h n-channel MOS transistors in first to h-th columns are located on a side of the silicon pillars close to the substrate, and are connected to one another via a silicide region, and   the n columns are grouped into g sets each having h columns, and the source regions of n-channel MOS transistors in a g-th set and the drain regions of n-channel MOS transistors in a (g+1)-th set are connected to one another.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein:
 the source regions of the n p-channel MOS transistors are connected to a power supply line extending along a row, and   the source regions of h n-channel MOS transistors in a last set among the g sets are connected to a reference power supply line extending along a row.   
     
     
         8 . The semiconductor device according to  claim 6 , wherein h n-channel MOS transistors grouped in the g-th set are arranged such that the source regions of n-channel MOS transistors in an even-numbered set are located on the side of the silicon pillars close to the substrate. 
     
     
         9 . The semiconductor device according to  claim 6 , wherein each of the g input signals is connected to gates of arbitrary h pairs of transistors among n sets of pairs of transistors whose gates are connected to one another. 
     
     
         10 . The semiconductor device according to  claim 7 , wherein each of the power supply line and the reference power supply line comprises a first metal line, and each of the g input signals comprises a second metal line extending in a direction perpendicular to the power supply line and the reference power supply line. 
     
     
         11 . A semiconductor device, comprising:
 a plurality of transistors arranged in m rows and n columns on a substrate, where m≧3 and n≧2, to constitute a NAND circuit, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate,   each of the plurality of transistors including:
 a silicon pillar, 
 an insulator surrounding a side surface of the silicon pillar, 
 a gate surrounding the insulator, 
 a source region disposed on an upper portion or a lower portion of the silicon pillar, and 
 a drain region disposed on an upper portion or a lower portion of the silicon pillar, the drain region being located on a side of the silicon pillar opposite to a side of the silicon pillar on which the source region is located, the plurality of transistors including:
 i×n p-channel MOS transistors arranged in i rows and n columns, and 
 j×n n-channel MOS transistors arranged in j rows and n columns, 
 
   wherein i+j=m, and   wherein the i×n p-channel MOS transistors and the j×n n-channel MOS transistors are arranged such that   i p-channel MOS transistors in a k-th column and j n-channel MOS transistors in the k-th column form a set, where k=1 to n, the gates of the i p-channel MOS transistors in the k-th column and the gates of the j n-channel MOS transistors in the k-th column being connected to one another,   the drain regions of the i×n p-channel MOS transistors and the drain regions of j n-channel MOS transistors in a first column are located on a side of the silicon pillars close to the substrate, the drain regions of the i×n p-channel MOS transistors and the drain regions of the j n-channel MOS transistors in the first column being connected to one another via a silicide region, and   the source regions of j n-channel MOS transistors in an s-th column and the drain regions of j n-channel MOS transistors in an (s+1)-th column are connected to one another, where s=1 to n−1.   
     
     
         12 . The semiconductor device according to  claim 11 , wherein:
 the source regions of the i×n p-channel MOS transistors are connected to a power supply line extending along a row, and   the source regions of j n-channel MOS transistors in an n-th column are connected to a reference power supply line extending along a row.   
     
     
         13 . The semiconductor device according to  claim 11 , wherein the j×n n-channel MOS transistors are arranged such that the source regions of j n-channel MOS transistors in an even-numbered column are located on the side of the silicon pillars close to the substrate. 
     
     
         14 . The semiconductor device according to  claim 11 , wherein n input signals are connected to gates of n sets of transistors whose gates are connected to one another so that each of the n input signals corresponds to gates of one of the n sets of transistors. 
     
     
         15 . The semiconductor device according to  claim 14 , wherein:
 the source regions of the i×n n-channel MOS transistors are connected to a reference power supply line extending along a row, and   the source regions of j p-channel MOS transistors in an n-th column are connected to a power supply line extending along a row,   each of the power supply line and the reference power supply line comprises a first metal line, and   each of the n input signals comprises a second metal line extending in a direction perpendicular to the power supply line and the reference power supply line.   
     
     
         16 . A semiconductor device, comprising:
 a plurality of transistors arranged in m rows and n columns on a substrate, where m≧2 and n≧2, to constitute a NAND circuit having g input signals, where n=h×g, g and h being each an integer, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate,   each of the plurality of transistors including:
 a silicon pillar, 
 an insulator surrounding a side surface of the silicon pillar, 
 a gate surrounding the insulator, 
 a source region disposed on an upper portion or a lower portion of the silicon pillar, and 
 a drain region disposed on an upper portion or a lower portion of the silicon pillar, the drain region being located on a side of the silicon pillar opposite to a side of the silicon pillar on which the source region is located, the plurality of transistors including: 
 i×n p-channel MOS transistors arranged in i rows and n columns, and 
 j×n n-channel MOS transistors arranged in j rows and n columns, 
   wherein i+j=m, and   wherein the i×n p-channel MOS transistors and the j×n n-channel MOS transistors are arranged such that   i p-channel MOS transistors in a k-th column and j n-channel MOS transistors in the k-th column form a set, where k=1 to n, the gates of the i p-channel MOS transistors in the k-th column and the gates of the j n-channel MOS transistors in the k-th column being connected to one another,   the drain regions of the i×n p-channel MOS transistors and the drain regions of j×h n-channel MOS transistors in first to h-th columns are located on a side of the silicon pillars close to the substrate,   the drain regions of the i×n p-channel MOS transistors and the drain regions of the j×h n-channel MOS transistors in the first to h-th columns are connected to one another via a silicide region, and   the n columns are grouped into g sets each having h columns, and the source regions of n-channel MOS transistors in a g-th set and the drain regions of n-channel MOS transistors in a (g+1)-th set are connected to one another.   
     
     
         17 . The semiconductor device according to  claim 16 , wherein:
 the source regions of the i×n p-channel MOS transistors are connected to a power supply line extending along a row, and   the source regions of h n-channel MOS transistors in a last set among the g sets are connected to a reference power supply line extending along a row.   
     
     
         18 . The semiconductor device according to  claim 16 , wherein j×n n-channel MOS transistors grouped in the g-th set are arranged such that the source regions of n-channel MOS transistors in an even-numbered set are located on a side of the silicon pillars close to the substrate. 
     
     
         19 . The semiconductor device according to  claim 16 , wherein each of the g input signals is connected to gates of arbitrary h sets of transistors among n sets of transistors whose gates are connected to one another, each of the n sets of transistors including i p-channel MOS transistors and j n-channel MOS transistors. 
     
     
         20 . The semiconductor device according to  claim 17 , wherein each of the power supply line and the reference power supply line comprises a first metal line, and each of the g input signals comprises a second metal line extending in a direction perpendicular to the power supply line and the reference power supply line. 
     
     
         21 . A semiconductor device, comprising:
 a plurality of transistors arranged in m rows and n columns on a substrate, where m≧2 and n≧2, to constitute a NAND circuit having g input signals, where n=h×g, g and h being each an integer, each of the plurality of transistors having a source, a drain, and a gate arranged in layers in a direction perpendicular to the substrate,   each of the plurality of transistors including:
 a silicon pillar, 
 an insulator surrounding a side surface of the silicon pillar, 
 a gate surrounding the insulator, 
 a source region disposed on an upper portion or a lower portion of the silicon pillar, and 
 a drain region disposed on an upper portion or a lower portion of the silicon pillar, the drain region being located on a side of the silicon pillar opposite to a side of the silicon pillar on which the source region is located, the plurality of transistors including: 
 i×n p-channel MOS transistors arranged in i rows and n columns, and 
 j×n n-channel MOS transistors arranged in j rows and n columns, 
   wherein i+j=m, and   wherein the i×n p-channel MOS transistors and the j×n n-channel MOS transistors are arranged such that   i p-channel MOS transistors in a k-th column and j n-channel MOS transistors in the k-th column form a set, where k=1 to n, the gates of the i p-channel MOS transistors in the k-th column and the gates of the j n-channel MOS transistors in the k-th column being connected to one another,   the source regions of the i×n p-channel MOS transistors and the source regions of j×h n-channel MOS transistors in first to h-th columns are located on a side of the silicon pillars close to the substrate,   the drain regions of the i×n p-channel MOS transistors and the drain regions of the j×h n-channel MOS transistors in the first to h-th columns are connected to one another via a contact, and   the n columns are grouped into g sets each having h columns, and the source regions of n-channel MOS transistors in a g-th set and the drain regions of n-channel MOS transistors in a (g+1)-th set are connected to one another.   
     
     
         22 . The semiconductor device according to  claim 21 , wherein:
 the source regions of the i×n p-channel MOS transistors are connected to a power supply line extending along a row, and   the source regions of h n-channel MOS transistors in a last set among the g sets are connected to a reference power supply line extending along a row.   
     
     
         23 . The semiconductor device according to  claim 21 , wherein j×n n-channel MOS transistors grouped in the g-th set are arranged such that the drain regions of n-channel MOS transistors in an even-numbered set are located on the side of the silicon pillars close to the substrate. 
     
     
         24 . The semiconductor device according to  claim 21 , wherein each of the g input signals is connected to gates of arbitrary h sets of transistors among n sets of transistors whose gates are connected to one another, each of the n sets of transistors including i p-channel MOS transistors and j n-channel MOS transistors. 
     
     
         25 . The semiconductor device according to  claim 22 , wherein each of the power supply line and the reference power supply line comprises a first metal line, and each of the g input signals comprises a second metal line extending in a direction perpendicular to the power supply line and the reference power supply line.