Flip chip package and manufacturing method thereof

Abstract

A flip chip package and a manufacturing method thereof are disclosed. The flip chip package in accordance with an embodiment of the present invention includes: a substrate; a plurality of pads formed on the substrate; a solder resist covering the substrate in such a way that the pads are exposed; a chip mounted on the substrate in such a way that the chip is electrically connected with the pads; a plurality of bumps formed, respectively, on the pads in such a way that the bumps are interposed between the pads and the chip; an under-fill flowing between the substrate and the chip and being filled in between the substrate and the chip; and an opening placed in between the plurality of bumps in such a way that a flowing space of the under-fill is provided in between the plurality of bumps.

What is claimed is: 
     
         1 . A flip chip package comprising:
 a substrate;   a plurality of pads formed on the substrate;   a solder resist covering the substrate in such a way that the pads are exposed;   a chip mounted on the substrate in such a way that the chip is electrically connected with the pads;   a plurality of bumps formed, respectively, on the pads in such a way that the bumps are interposed between the pads and the chip; and   an under-fill flowing between the substrate and the chip and being filled in between the substrate and the chip,   wherein the solder resist comprises an opening placed in between the plurality of bumps in such a way that a flowing space of the under-fill is provided in between the plurality of bumps.   
     
     
         2 . The flip chip package of  claim 1 , further comprising an inner material layer formed inside the opening, and
 wherein a wettability of the under-fill for the inner material layer is greater than a wettability of the under-fill for the solder resist.   
     
     
         3 . The flip chip package of  claim 2 , wherein the inner material layer is made of a metal. 
     
     
         4 . The flip chip package of  claim 2 , wherein the inner material layer is formed to be separated from the pads. 
     
     
         5 . The flip chip package of  claim 2 , further comprising a connecting part for connecting at least two of the pads with one another, and
 wherein the inner material layer is formed to be separated from the connecting part.   
     
     
         6 . The flip chip package of  claim 2 , wherein the inner material layer is covered by the solder resist and then exposed by the opening. 
     
     
         7 . The flip chip package of  claim 1 , wherein the under-fill is dispensed to one side of the substrate and then flows to the other side of the substrate. 
     
     
         8 . The flip chip package of  claim 1 , wherein the opening is extended in a flowing direction of the under-fill. 
     
     
         9 . The flip chip package of  claim 8 , wherein the opening is formed in a disconnected fashion. 
     
     
         10 . The flip chip package of  claim 7 , wherein one end of the opening is extended to an area of the substrate where the under-fill is dispensed. 
     
     
         11 . The flip chip package of  claim 10 , wherein the other end of the opening is extended to an outside area of the chip. 
     
     
         12 . A method of manufacturing a flip chip package, comprising:
 forming a plurality of pads on a substrate;   forming a solder resist on the substrate so as to cover the pads;   removing portions of the solder resist so as to expose the pads;   forming an opening by removing a portion of the solder resist arranged in between the plurality of pads;   mounting a chip, which has a plurality of bumps thereon, on the substrate in such a way that the bumps are in contact, respectively, with the pads; and   filling a space between the substrate and the chip with an under-fill by flowing the under-fill in between the plurality of bumps.   
     
     
         13 . The method of  claim 2 , wherein the forming of the plurality of pads on the substrate comprises forming an inner material layer on the substrate in such a way that the inner material layer is arranged in between the plurality of pads,
 wherein the solder resist covers the pads and the inner material layer,   wherein the inner material layer is exposed by the opening,   a wettability of the under-fill for the inner material layer is greater than a wettability of the under-fill for the solder resist.   
     
     
         14 . The method of  claim 13 , wherein the inner material layer is made of a metal. 
     
     
         15 . The method of  claim 13 , wherein the inner material layer is formed to be separated from the pads. 
     
     
         16 . The method of  claim 13 , wherein the forming of the plurality of pads on the substrate further comprises forming a connecting part on the substrate for connecting at least two of the pads with one another, and
 wherein the inner material layer is formed to be separated from the connecting part.   
     
     
         17 . The method of  claim 12 , wherein the filling of the space between the substrate and the chip with the under-fill comprises:
 dispensing the under-fill to one side of the substrate; and   allowing the under-fill to flow to the other side of the substrate.   
     
     
         18 . The method of  claim 17 , wherein the opening is extended in a flowing direction of the under-fill. 
     
     
         19 . The method of  claim 18 , wherein one end of the opening is extended to an area of the substrate where the under-fill is dispensed. 
     
     
         20 . The method of  claim 19 , wherein the other end of the opening is extended to an outside area of the chip.