Method and System for Secure System-on-a-Chip Architecture for Multimedia Data Processing

Abstract

Aspects of a method and apparatus for a secure system-on-a-chip (SOC) architecture for multimedia data processing are provided. A processor may configure at least one subsystem within the SOC via at least one unsecured bus while a security processor enables secure functionalities in configured subsystems via at least one secure bus. The unsecure buses may comprise a data bus and/or a control bus, for example. The secure buses may comprise a secure control bus and/or a secure key bus, for example. The configurable subsystems may be multimedia processing units, input and output modules, and/or memory controllers. The security processor may program bits in security registers within the subsystems to enable secure functionalities, such as data routing paths and/or key loading paths, for example. Moreover, the security processor may validate code to be executed by a processor for configuring the SOC subsystems.

What is claimed is: 
     
         1 . A method for enabling a multimedia routing path, the method comprising:
 configuring, by a first processor, a descrambling block of a plurality of subsystems by writing to a configuration register to select an input source and an output destination for the descrambling block;   validating the selected input source and the selected output destination for the descrambling block by writing to a security register by a second processor; and   writing to the security register to indicate a type of descrambling to be performed.   
     
     
         2 . The method according to  claim 1 , wherein the plurality of subsystems comprises:
 a multimedia processing unit.   
     
     
         3 . The method according to  claim 1 , wherein the plurality of subsystems comprises:
 an input and output module.   
     
     
         4 . The method according to  claim 1 , wherein the plurality of subsystems comprises:
 a memory controller.   
     
     
         5 . The method according to  claim 1 , wherein writing to the security register comprises:
 writing a bit in the security register.   
     
     
         6 . The method according to  claim 1 , further comprising:
 validating code to be executed by the first processor by the second processor.   
     
     
         7 . The method according to  claim 6 , further comprising:
 enabling the first processor to configure the descrambling block after validating the code.   
     
     
         8 . A system, comprising:
 a first processor configured to configure a descrambling block of a plurality of subsystems by writing to a configuration register to select an input source and an output destination for the descrambling block; and   a second processor configured to validate the selected input source and the selected output destination for the descrambling block by writing to a security register and to indicate a type of descrambling to be performed by writing to the security register.   
     
     
         9 . The system according to  claim 8 , wherein the plurality of subsystems comprises:
 a multimedia processing unit.   
     
     
         10 . The system according to  claim 8 , wherein the plurality of subsystems comprises:
 an input and output module.   
     
     
         11 . The system according to  claim 8 , wherein the plurality of subsystems comprises:
 a memory controller.   
     
     
         12 . The system according to  claim 8 , wherein the second processor is configured to validate the selected input source and the selected output destination by writing a bit in the security register. 
     
     
         13 . The system according to  claim 8 , wherein the second processor is further configured to validate code to be executed by the first processor. 
     
     
         14 . The system according to  claim 13 , wherein the first processor is configured to enable configuration of the descrambling block after the second processor has validated the code. 
     
     
         15 . A non-transitory machine-readable storage having stored thereon a computer program for enabling a multimedia routing path, the computer program being executable by a machine for causing the machine to:
 configure a descrambling block of a plurality of subsystems by writing to a configuration register to select an input source and an output destination for the descrambling block;   validate the selected input source and the selected output destination for the descrambling block by writing to a security register by a security processor; and   indicate a type of descrambling to be performed by writing to the security register.   
     
     
         16 . The non-transitory machine-readable storage according to  claim 15 , wherein the plurality of subsystems comprises:
 a multimedia processing unit.   
     
     
         17 . The non-transitory machine-readable storage according to  claim 15 , wherein the plurality of subsystems comprises:
 an input and output module.   
     
     
         18 . The non-transitory machine-readable storage according to  claim 15 , wherein the plurality of subsystems comprises:
 a memory controller.   
     
     
         19 . The non-transitory machine-readable storage according to  claim 15 , wherein the computer program is executable by the machine for causing the machine to validate the selected input source and the selected output destination by writing a bit in the security register. 
     
     
         20 . The non-transitory machine-readable storage according to  claim 15 , wherein the computer program is executable by the machine for causing the machine to validate code to be executed by a processor by the security processor.