Method and system for organizing pixel information in memory
Abstract
A system and method for organizing pixel information in memory. A method according to an embodiment of the disclosure includes storing data representative of pixels of a scene in a growing window (“GW”) portion of a reference frame in an on-chip memory, storing data representative of pixels of the visual scene in a sliding window (“SW”) portion of the reference frame thereby forming a hybrid window, searching the memory to locate a portion of the stored data that corresponds with data representative of pixels in a current frame descriptive of the scene, performing motion estimation according to results of the search, generating a compressed version of the current frame according to results of the motion estimation, and storing the compressed version for later visual rendering. The system includes a processing unit and a video encoder. The processing unit includes an on-chip memory. The video encoder includes a motion estimation engine and a compression unit.
Claims
exact text as granted — not AI-modifiedWhat is claimed is:
1 . A video processor comprising:
an input port for receiving a video signal formed of frames of data; a discrete cosine transform unit coupled to the input port, the discrete cosine transform unit converting the video signal from a spatial domain signal to a frequency domain output signal; a quantization unit coupled to the output signal of the discrete cosine transform unit, the quantization unit constraining values in a continuous set of values to a discrete set of output values; an encoding unit coupled to the output values of the quantization unit and coupled to motion vector outputs to generate an encoded video bit stream output; an inverse quantization unit coupled to the output values of the quantization unit, the inverse quantization unit producing inverse output signals that are an inverse of the output values of the quantization unit; an inverse discrete cosine transform unit coupled to the inverse output signals, the inverse discrete cosine transform unit producing reconstructed residual video output signals; a motion estimation engine coupled to the input port, the motion estimation engine producing motion vector outputs from a comparison of a frame of data from the video signal with a reference frame of data, the motion vector outputs being coupled to the encoding unit; a motion compensation unit coupled to the motion vector outputs and to the reference frame of data and producing motion compensation outputs; an adder coupled to the residual video output signals and the motion compensation outputs to provide reconstructed video signals; and an on-chip memory coupled to the reconstructed video signals for storing the reconstructed video signals as the reference frame of data, the on-chip memory being coupled to the motion estimation unit and the motion compensation unit.
2 . The video processor of claim 1 including a subtractor selectively coupling the discrete cosine transform unit to the input port and to motion vector outputs from the motion compensation engine.
3 . The video processor of claim 1 including an external memory coupled to the reconstructed video signals for storing the reconstructed video signals as the reference frame of data, the external memory being coupled to the on-chip memory.
4 . The video processor of claim 1 including:
a compression unit coupled to the reconstructed video signals from the adder and providing a compressed frame and an error frame output, the error frame representing a difference between a reference frame and the compressed frame, and
a decompression unit coupled to the compressed frame and error frame output and providing the reference frame to the on-chip memory.
5 . The video processor of claim 1 including an external memory coupled to the reconstructed video signals for storing the reconstructed video signals as the reference frame of data, the external memory being coupled to the decompression unit.Join the waitlist — get patent alerts
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