Integrated circuits with dual silicide contacts and methods for fabricating same

Abstract

Integrated circuits with dual silicide contacts are provided. In an embodiment, an integrated circuit includes a semiconductor substrate including a first area and a second area. The integrated circuit includes a first source/drain region in and/or overlying the first area of the semiconductor substrate and a second source/drain region in and/or overlying the second area of the semiconductor substrate. The integrated circuit further includes a first contact over the first source/drain region and comprising a first metal silicide. The integrated circuit also includes a second contact over the second source/drain region and comprising a second metal silicide different from the first metal silicide.

What is claimed is: 
     
         1 . An integrated circuit comprising:
 a semiconductor substrate including a first area and a second area;   a first source/drain region in and/or overlying the first area of the semiconductor substrate;   a second source/drain region in and/or overlying the second area of the semiconductor substrate;   a first contact over the first source/drain region and comprising a first metal silicide; and   a second contact over the second source/drain region and comprising a second metal silicide different from the first metal silicide.   
     
     
         2 . The integrated circuit of  claim 1  wherein the second metal silicide is formed from a second metal, and wherein the integrated circuit further comprises a layer of the second metal over the first contact. 
     
     
         3 . The integrated circuit of  claim 2  further comprising a metal fill material overlying the layer of second metal over the first contact and overlying the second contact. 
     
     
         4 . The integrated circuit of  claim 2  wherein the first metal silicide is platinum silicide, wherein the second metal silicide is titanium silicide, and wherein the second metal includes titanium. 
     
     
         5 . The integrated circuit of  claim 4  wherein the second metal includes a layer of titanium and a capping layer of titanium nitride. 
     
     
         6 . The integrated circuit of  claim 4  wherein the second metal includes a layer of titanium and cobalt and a capping layer of titanium nitride. 
     
     
         7 . The integrated circuit of  claim 4  wherein the metal fill material is tungsten. 
     
     
         8 . The integrated circuit of  claim 1  wherein the first metal silicide is on the first source/drain region and the second metal silicide is on the second source/drain region. 
     
     
         9 . The integrated circuit of  claim 8  wherein the second metal silicide is formed from a second metal, and wherein the integrated circuit further comprises a layer of the second metal on the first contact. 
     
     
         10 . The integrated circuit of  claim 9  further comprising a metal fill material, wherein a first portion of the metal fill material is on the layer of second metal on the first contact and a second portion of the metal fill material is on the second contact. 
     
     
         11 . The integrated circuit of  claim 8  wherein the second metal silicide is formed from a second metal, and wherein the integrated circuit further comprises:
 a layer of the second metal on the first contact; and 
 a capping layer on the layer of the second metal on the first contact and on the second metal silicide. 
 
     
     
         12 . The integrated circuit of  claim 11  further comprising a metal fill material, wherein a first portion of the metal fill material is on the capping layer on the layer of second metal on the first contact and a second portion of the metal fill material is on the capping layer on the second metal silicide. 
     
     
         13 . The integrated circuit of  claim 1  wherein the first area is a PFET area and the second area is an NFET area. 
     
     
         14 . An integrated circuit comprising:
 a semiconductor substrate including a PFET area and an NFET area;   a PFET gate structure interposed between source/drain regions in the PFET area;   an NFET gate structure interposed between source/drain regions in the NFET area;   first contacts on the source/drain regions in the PFET area, wherein the first contacts are a first metal silicide;   second contacts on the source/drain regions in the NFET area, wherein the second contacts are a second metal silicide different from the first metal silicide; and   a second metal layer, wherein first portions of the second metal layer are overlying the first contacts and second portions of the second metal layer are overlying the second contacts, and wherein the second metal silicide is formed from the second portions of the second metal layer.   
     
     
         15 . The integrated circuit of  claim 14  further comprising:
 a dielectric material overlying the contacts and gate structures; 
 an electrical gate contact in electrical connection with a selected gate structure; and 
 an electrical source/drain contact in electrical connection with a selected contact. 
 
     
     
         16 . The integrated circuit of  claim 14  further comprising a metal fill material overlying the first portions and second portions of the second metal layer. 
     
     
         17 . The integrated circuit of  claim 16  wherein the first metal silicide is platinum silicide, wherein the second metal silicide is titanium silicide, and wherein the second metal includes titanium. 
     
     
         18 . The integrated circuit of  claim 17  wherein the second metal layer includes titanium and a capping layer of titanium nitride. 
     
     
         19 . The integrated circuit of  claim 16  wherein the metal fill material is tungsten. 
     
     
         20 . An integrated circuit comprising:
 a semiconductor substrate having PFET areas and NFET areas;   first contacts over the semiconductor substrate in the PFET areas, wherein the first contacts are a first metal silicide; and   second contacts over the semiconductor substrate in the NFET areas, wherein the second contacts are a second metal silicide different from the first metal silicide.