Self-organizing network with chip package having multiple interconnection configurations

Abstract

In general, embodiments of the present invention provide a chip package with multiple TSV configurations. Specifically, the chip package typically includes a backend layer (e.g., metal interconnect layer); a substrate coupled to the backend layer; a set (at least one) of backend side interconnects extending (e.g., angularly) from a side surface of the backend layer to a bottom surface of the backend layer; a set of optional vertical TSVs extending from a top surface of the backend layer through the substrate; and a network organizer positioned in the substrate organizer for handling communications made using the set of backend side interconnects and the set of vertical TSVs. A set of connections (e.g., controlled collapse chip connections (C4s) can be positioned adjacent to any of the vias to provide connectively to other hardware elements such as additional chip packages, buses, etc. Among other things, the use of backend side interconnects allows maximum surface area of the chip package to be utilized and provides increased reliability. These advantages are especially realized when used in conjunction with vertical TSVs.

What is claimed is: 
     
         1 . A set of chip packages comprising:
 a first chip comprising:
 a first backend layer, 
 a first substrate coupled to the first backend layer, 
 a first set of backend side interconnects angularly extending continually between a side surface of the first backend layer to terminate at a bottom surface of the first backend layer, wherein the bottom surface of the first backend layer is substantially perpendicular to the side surface of the first backend layer, wherein a top surface of the first backend layer substantially covers a top surface of the set of backend side interconnects, and 
 a controlled collapse chip connection (C4) positioned along a side surface of the first backend layer, adjacent to one of the first set of backend side interconnects, disposed for coupling the chip package to 
   a hardware element; and   a second chip comprising:
 a second backend layer, 
 a second substrate coupled to the second backend layer, 
 a second set of backend side interconnects angularly extending continually between a side surface of the second backend layer to terminate at a bottom surface of the second backend layer, wherein the bottom surface of the second backend layer is substantially perpendicular to the side surface of the second backend layer, wherein a top surface of the first backend layer substantially covers a top surface of the set of backend side interconnects, and 
 a second controlled collapse chip connection (C4) positioned along a side surface of the second backend layer, adjacent to one of the second set of backend side interconnects, disposed for coupling the chip package to a hardware element. 
   
     
     
         2 . The set of chip packages of  claim 1 , further comprising a third C4 positioned between the first and second backend layer, adjacent to one of the backend side interconnects of each of the first and second backend layers, the third C4 being for coupling the first and second chip package to another. 
     
     
         3 . The set of chip packages of  claim 2 , wherein:
 the first chip further comprises a third set of backend side interconnects angularly extending continually between the side surface of the first backend layer to terminate at the bottom surface of the first backend layer, and   the second chip further comprises a fourth set of backend side interconnects angularly extending continually between the side surface of the second backend layer to terminate at the bottom surface of the second backend layer.   
     
     
         4 . The set of chip packages of  claim 3 , further comprising a fourth C4 positioned between the first and second backend layer, between one of the third backend side interconnects and one of the fourth backend side interconnects. 
     
     
         5 . The set of chip packages of  claim 1 , further comprising;
 a first network organizer for handling communications made using the first set of backend side interconnects; and   a second network organizer for handling communications made using the second set of backend side interconnects.   
     
     
         6 . The set of chip packages of  claim 5 , the first network organizer being positioned in the first substrate, and the second network organizer being positioned in the second substrate. 
     
     
         7 . The chip package of  claim 5 , the network organizers being configured to provide bandwidth for the communications based on a power budget. 
     
     
         8 . The set of chip packages of  claim 1 ,
 wherein the first backend layer and the first substrate are separate layers from one another; and   wherein the second backend layer and the second substrate are separate layers from one another.   
     
     
         9 . The set of chip packages of  claim 1 , the first chip further comprising a first set of vertical through silicon vias (TSVs) extending from the top surface of the first backend layer to a bottom surface of the first substrate. 
     
     
         10 . A set of chip packages comprising:
 a first chip comprising:
 a first backend layer, 
 a first substrate coupled to the first backend layer, and 
 a set of vertical through silicon vias (TSVs) extending from the top surface of the first backend layer to a bottom surface of the first substrate, wherein the bottom surface of the first backend layer is substantially perpendicular to the side surface of the first backend layer; and 
   a second chip comprising:
 a second backend layer, 
 a second substrate coupled to the second backend layer, 
 a set of backend top interconnects extending continually between a top surface of the second backend layer to terminate at a bottom surface of the second backend layer, wherein the bottom surface of the second backend layer is substantially perpendicular to the side surface of the second backend layer and substantially parallel to the top surface of the second backend layer, and 
 a set of controlled collapse chip connections (C4s) positioned along the top surface of the second backend layer, adjacent to the second set of backend top interconnects. 
   
     
     
         11 . The set of chip packages of  claim 10 , the first chip further comprising a set of backend side interconnects angularly extending continually between a side surface of the first backend layer to terminate at the bottom surface of the first backend layer. 
     
     
         12 . The set of chip packages of  claim 11 , further comprising a second set of C4s positioned along the side surface of the first backend layer, adjacent the set of backend side interconnects. 
     
     
         13 . The set of chip packages of  claim 10 , further comprising;
 a first network organizer positioned in the first substrate for handling communications made using the set of vertical TSVs; and   a second network organizer positioned in the second substrate for handling communications made using the set of backend top interconnects   
     
     
         14 . A method for manufacturing a set of chip packages comprising:
 providing a first backend layer;   coupling a first substrate to the first backend layer;   providing a first set of backend side interconnects extending from a side surface of the first backend layer through a bottom surface of the first backend layer;   providing a second backend layer;   coupling a second substrate to the second backend layer;   providing a second set of backend side interconnects extending from a side surface of the second backend layer through a bottom surface of the second backend layer;   coupling one of the first backend side interconnects to one of the second backend side interconnects via a controlled collapse chip connections (C4s); and   providing a set of controlled collapse chip connections (C4s) positioned along outer side surfaces of the first and second backend layers, adjacent to the first and second backend side interconnects, disposed for coupling the set of chip packages to a hardware element.   
     
     
         15 . The method of  claim 14 , further comprising providing a set of vertical through silicon vias (TSVs) extending from a top surface of the first backend layer through the first substrate. 
     
     
         16 . The method of  claim 15 , at least one of the set of backed side interconnects and at least one of the set of vertical TSVs interconnecting one another. 
     
     
         17 . The method of  claim 14 , further comprising:
 positioning a first set of controlled collapse chip connections (C4s) along the substrate, adjacent the set of vertical TSVs; and   positioning a C4 along a side surface of the first and second backend layer, adjacent to the set of backend side interconnects.   
     
     
         18 . The method of  claim 17 , the first set of C4s being for coupling the chip package to at least one other chip package. 
     
     
         19 . The method of  claim 14 , further comprising providing a network organizer for handling communications made between at least one chip package and at least one other chip package. 
     
     
         20 . The method of  claim 19 , the network organizer being positioned in the substrate.