Semiconductor integrated circuit device

Abstract

A semiconductor integrated circuit device has, as a current monitor circuit, a circuit in which n-channel type MISFETs are connected in series with each other. Based on a delay time of a speed monitor circuit in a state where a substrate bias is being applied to the p-channel type MISFETs, a first voltage value of a first substrate bias to be applied to the p-channel type MISFETs is determined. Next, based on a current flowing through an n-channel type MISFET in a state where the first substrate bias is being applied to the p-channel type MISFETs of the current monitor circuit and a second substrate bias is being applied to the n-channel type MISFETs of the current monitor circuit, a second voltage value of the second substrate bias to be applied to the n-channel type MISFETs is determined.

1 . A semiconductor integrated circuit device comprising:
 a main circuit having a first MISFET of a first channel type, a second MISFET of a second channel type different from the first channel type and a third MISFET of the second channel type which is connected in series with the second MISFET; and   a control circuit which executes control so as to apply a first substrate bias voltage to the first MISFET and apply a second substrate bias voltage to the second MISFET and the third MISFET,   wherein the control circuit comprises:   a first delay circuit having a first inverter circuit including a fourth MISFET of the first channel type;   a first current monitor circuit which includes a fifth MISFET of the first channel type, a sixth MISFET of the second channel type and a seventh MISFET of the second channel type connected in series with the sixth MISFET, and monitors a first current flowing through the fifth MISFET and a second current flowing through the sixth MISFET and the seventh MISFET; and   a voltage generating circuit for generating the first substrate bias voltage and the second substrate bias voltage, and   the control circuit makes the voltage generating circuit generate the first substrate bias voltage and apply it to the fourth MISFET,   determines a first voltage value of the first substrate bias voltage based on a first delay time of the first delay circuit in a state where the first substrate bias voltage is being applied to the fourth MISFET,   makes the voltage generating circuit generate the first substrate bias voltage set to the first voltage value and apply it to the fifth MISFET,   acquires, by the first current monitor circuit, the first current flowing through the fifth MISFET in a state where the first substrate bias voltage set to the first voltage value is being applied thereto,   makes the voltage generating circuit generate the second substrate bias voltage and apply it to the sixth MISFET and the seventh MISFET,   acquires, by the first current monitor circuit, the second current flowing through the sixth MISFET and the seventh MISFET in a state where the second substrate bias voltage is being applied thereto,   determines a second voltage value of the second substrate bias voltage based on the acquired first current and the acquired second current, and   makes the voltage generating circuit generate the first substrate bias voltage set to the first voltage value and apply it to the first MISFET, and makes the voltage generating circuit generate the second substrate bias voltage set to the second voltage value and apply it to the second MISFET and the third MISFET.   
     
     
         2 . The semiconductor integrated circuit device according to  claim 1 ,
 wherein the control circuit determines the first voltage value so that the first delay time becomes a second target time different from a first target time of a second delay time of the main circuit, and   determines the second voltage value so that a first calculated value calculated as a sum of reciprocals of the respective acquired first current and acquired second current becomes a first set value determined in accordance with the first target time.   
     
     
         3 . The semiconductor integrated circuit device according to  claim 1 ,
 wherein the first channel type is a p-channel type,   the second channel type is an n-channel type,   the main circuit has a NAND circuit, and   the NAND circuit includes the first MISFET, the second MISFET, the third MISFET and a p-channel type eighth MISFET connected in parallel with the first MISFET.   
     
     
         4 . The semiconductor integrated circuit device according to  claim 3 ,
 wherein a source electrode of the fifth MISFET is connected to a power supply,   a drain electrode of the fifth MISFET is grounded,   a drain electrode of the sixth MISFET is connected to the power supply,   a source electrode of the sixth MISFET is connected to a drain electrode of the seventh MISFET, and   a source electrode of the seventh MISFET is grounded.   
     
     
         5 . The semiconductor integrated circuit device according to  claim 3 , further comprising:
 a first substrate;   an n-type first semiconductor region formed on a first main surface side of the first substrate in a first area on the first main surface side of the first substrate;   a p-type second semiconductor region formed on the first main surface side of the first substrate in a second area on the first main surface side of the first substrate;   a first insulating layer formed on the first semiconductor region in the first area;   a second insulating layer formed on the second semiconductor region in the second area;   a first semiconductor layer formed on the first insulating layer; and   a second semiconductor layer formed on the second insulating layer,   wherein the first MISFET, the fourth MISFET and the fifth MISFET are formed on the first semiconductor layer,   the second MISFET, the third MISFET, the sixth MISFET and the seventh MISFET are formed on the second semiconductor layer,   the first substrate bias voltage is applied to the first semiconductor region, and   the second substrate bias voltage is applied to the second semiconductor region.   
     
     
         6 . The semiconductor integrated circuit device according to  claim 1 ,
 wherein the first channel type is an n-channel type,   the second channel type is a p-channel type,   the main circuit has a NOR circuit, and   the NOR circuit includes the first MISFET, the second MISFET, the third MISFET and an n-channel type ninth MISFET connected in parallel with the first MISFET.   
     
     
         7 . The semiconductor integrated circuit device according to  claim 6 ,
 wherein a drain electrode of the fifth MISFET is connected to a power supply,   a source electrode of the fifth MISFET is grounded,   a source electrode of the sixth MISFET is connected to the power supply,   a drain electrode of the sixth MISFET is connected to a source electrode of the seventh MISFET, and   a drain electrode of the seventh MISFET is grounded.   
     
     
         8 . The semiconductor integrated circuit device according to  claim 6 , further comprising:
 a second substrate;   a p-type third semiconductor region formed on a second main surface side of the second substrate in a third area on the second main surface side of the second substrate;   an n-type fourth semiconductor region formed on the second main surface side of the second substrate in a fourth area on the second main surface side of the second substrate;   a third insulating layer formed on the third semiconductor region in the third area;   a fourth insulating layer formed on the fourth semiconductor region in the fourth area;   a third semiconductor layer formed on the third insulating layer; and   a fourth semiconductor layer formed on the fourth insulating layer,   wherein the first MISFET, the fourth MISFET and the fifth MISFET are formed on the third semiconductor layer,   the second MISFET, the third MISFET, the sixth MISFET and the seventh MISFET are formed on the fourth semiconductor layer,   the first substrate bias voltage is applied to the third semiconductor region, and   the second substrate bias voltage is applied to the fourth semiconductor region.   
     
     
         9 . The semiconductor integrated circuit device according to  claim 1 ,
 wherein the first inverter circuit is a CMIS inverter circuit including the fourth MISFET and a tenth MISFET of the second channel type, and   the first delay circuit includes a plurality of the first inverter circuits connected in series with each other.   
     
     
         10 . The semiconductor integrated circuit device according to  claim 9 ,
 wherein the first delay circuit is a ring oscillator circuit provided with three or more odd-numbered first inverter circuits connected in series with each other.   
     
     
         11 . The semiconductor integrated circuit device according to  claim 1 ,
 wherein the first current monitor circuit includes an eleventh MISFET of the second channel type, a twelfth MISFET of the second channel type, a thirteenth MISFET of the second channel type connected in series with the twelfth MISFET and a fourteenth MISFET of the second channel type connected in series with the twelfth MISFET and the thirteenth MISFET, and monitors a third current flowing through the eleventh MISFET and a fourth current flowing through the twelfth MISFET, the thirteenth MISFET and the fourteenth MISFET, and   the control circuit determines a third voltage value of the second substrate bias voltage based on the acquired first current and the acquired second current,   makes the voltage generating circuit generate the second substrate bias voltage and apply it to the eleventh MISFET,   acquires, by the first current monitor circuit, the third current flowing through the eleventh MISFET in a state where the second substrate bias voltage is being applied thereto,   determines a fourth voltage value of the second substrate bias voltage based on the acquired first current and the acquired third current,   makes the voltage generating circuit generate the second substrate bias voltage and apply it to the twelfth MISFET, the thirteenth MISFET and the fourteenth MISFET,   acquires, by the first current monitor circuit, the fourth current flowing through the twelfth MISFET, the thirteenth MISFET and the fourteenth MISFET in a state where the second substrate bias voltage is being applied thereto,   determines a fifth voltage value of the second substrate bias voltage based on the acquired first current and the acquired fourth current, and   determines the second voltage value based on the third voltage value, the fourth voltage value and the fifth voltage value.   
     
     
         12 . The semiconductor integrated circuit device according to  claim 1 ,
 wherein the main circuit includes a fifteenth MISFET of the first channel type, a sixteenth MISFET of the second channel type and a seventeenth MISFET of the second channel type connected in series with the sixteenth MISFET,   the control circuit executes control so as to apply a third substrate bias voltage to the fifteenth MISFET and apply a fourth substrate bias voltage to the sixteenth MISFET and the seventeenth MISFET,   the control circuit comprises: a second delay circuit provided with a second inverter circuit including an eighteenth MISFET of the first channel type; and   a second current monitor circuit which includes a nineteenth MISFET of the first channel type, a twentieth MISFET of the second channel type, a twenty-first MISFET of the second channel type connected in series with the twentieth MISFET, and monitors a fifth current flowing through the nineteenth MISFET and a sixth current flowing through the twentieth MISFET and the twenty-first MISFET,   the voltage generating circuit generates the third substrate bias voltage and the fourth substrate bias voltage,   absolute values of threshold voltages of the first MISFET, the fourth MISFET and the fifth MISFET are larger than any of absolute values of threshold voltages of the fifteenth MISFET, the eighteenth MISFET and the nineteenth MISFET,   absolute values of threshold voltages of the second MISFET, the third MISFET, the sixth MISFET and the seventh MISFET are larger than any of absolute values of threshold voltages of the sixteenth MISFET, the seventeenth MISFET, the twentieth MISFET and the twenty-first MISFET, and   the control circuit makes the voltage generating circuit generate the third substrate bias voltage and apply it to the eighteenth MISFET,   determines a sixth voltage value of the third substrate bias voltage based on a third delay time of the second delay circuit in a state where the third substrate bias voltage is being applied to the eighteenth MISFET,   makes the voltage generating circuit generate the third substrate bias voltage set to the sixth voltage value and apply it to the nineteenth MISFET,   acquires, by the second current monitor circuit, the fifth current flowing through the nineteenth MISFET in a state where the third substrate bias voltage set to the sixth voltage value is being applied thereto,   makes the voltage generating circuit generate the fourth substrate bias voltage and apply it to the twentieth MISFET and the twenty-first MISFET,   acquires, by the second current monitor circuit, the sixth current flowing through the twentieth MISFET and the twenty-first MISFET in a state where the fourth substrate bias voltage is being applied thereto,   determines a seventh voltage value of the fourth substrate bias voltage based on the acquired fifth current and the acquired sixth current, and   makes the voltage generating circuit generate the third substrate bias voltage set to the sixth voltage value and apply it to the fifteenth MISFET, and makes the voltage generating circuit generate the fourth substrate bias voltage set to the seventh voltage value and apply it to the sixteenth MISFET and the seventeenth MISFET.   
     
     
         13 . The semiconductor integrated circuit device according to  claim 12 , further comprising:
 a third substrate;   a fifth semiconductor region of a first conductivity type formed on a third main surface side of the third substrate in a fifth area on the third main surface side of the third substrate and a sixth area on the third main surface side of the third substrate and adjacent to the fifth area;   a sixth semiconductor region of a second conductivity type different from the first conductivity type formed on the third main surface side of the third substrate in a seventh area on the third main surface side of the third substrate and an eighth area on the third main surface side of the third substrate and adjacent to the seventh area;   a seventh semiconductor region of the first conductivity type formed in an upper layer portion of the fifth semiconductor region in the fifth area;   an eighth semiconductor region of the first conductivity type formed in an upper layer portion of the fifth semiconductor region in the sixth area;   a ninth semiconductor region of the second conductivity type formed in an upper layer portion of the sixth semiconductor region in the seventh area;   a tenth semiconductor region of the second conductivity type formed in an upper layer portion of the sixth semiconductor region in the eighth area;   a fifth insulating layer formed on the seventh semiconductor region and the eighth semiconductor region;   a sixth insulating layer formed on the ninth semiconductor region and the tenth semiconductor region;   a fifth semiconductor layer formed on the fifth insulating layer in the fifth area and the sixth area; and   a sixth semiconductor layer formed on the sixth insulating layer in the seventh area and the eighth area,   wherein the first MISFET, the fourth MISFET and the fifth MISFET are formed on the fifth semiconductor layer in the fifth area,   the fifteenth MISFET, the eighteenth MISFET and the nineteenth MISFET are formed on the fifth semiconductor layer in the sixth area,   the second MISFET, the third MISFET, the sixth MISFET and the seventh MISFET are formed on the sixth semiconductor layer in the seventh area,   the sixteenth MISFET, the seventeenth MISFET, the twentieth MISFET and the twenty-first MISFET are formed on the sixth semiconductor layer in the eighth area,   an impurity concentration of the first conductivity type in the seventh semiconductor region is higher than an impurity concentration of the first conductivity type in the eighth semiconductor region,   an impurity concentration of the second conductivity type in the ninth semiconductor region is higher than an impurity concentration of the second conductivity type in the tenth semiconductor region,   when the first conductivity type is an n-type and the second conductivity type is a p-type, the first channel type is a p-channel type and the second channel type is an n-channel type, and   when the first conductivity type is a p-type and the second conductivity type is an n-type, the first channel type is an n-channel type and the second channel type is a p-channel type.   
     
     
         14 . A semiconductor integrated circuit device comprising:
 a main circuit having a first MISFET of a first channel type, a second MISFET of a second channel type different from the first channel type and a third MISFET of the second channel type which is connected in series with the second MISFET; and   a control circuit which executes control so as to apply a first substrate bias voltage to the first MISFET and apply a second substrate bias voltage to the second MISFET and the third MISFET,   wherein the control circuit comprises:   a first delay circuit having a first inverter circuit including a fourth MISFET of the first channel type;   a second delay circuit having a second inverter circuit including a fifth MISFET of the second channel type and a sixth MISFET of the second channel type connected in series with the fifth MISFET; and   a voltage generating circuit for generating the first substrate bias voltage and the second substrate bias voltage,   the control circuit makes the voltage generating circuit generate the first substrate bias voltage and apply it to the fourth MISFET,   determines a first voltage value of the first substrate bias voltage based on a first delay time of the first delay circuit in a state where the first substrate bias voltage is being applied to the fourth MISFET,   makes the voltage generating circuit generate the second substrate bias voltage and apply it to the fifth MISFET and the sixth MISFET,   determines a second voltage value of the second substrate bias voltage based on a second delay time of the second delay circuit in a state where the second substrate bias voltage is being applied to the fifth MISFET and the sixth MISFET, and   makes the voltage generating circuit generate the first substrate bias voltage set to the first voltage value and apply it to the first MISFET, and makes the voltage generating circuit generate the second substrate bias voltage set to the second voltage value and apply it to the second MISFET and the third MISFET.   
     
     
         15 . The semiconductor integrated circuit device according to  claim 14 ,
 wherein the first channel type is a p-channel type,   the second channel type is an n-channel type,   the main circuit has a NAND circuit, and   the NAND circuit includes the first MISFET, the second MISFET, the third MISFET and a p-channel type seventh MISFET connected in parallel with the first MISFET.   
     
     
         16 . The semiconductor integrated circuit device according to  claim 15 , further comprising:
 a first substrate;   an n-type first semiconductor region formed on a first main surface side of the first substrate in a first area on the first main surface side of the first substrate;   a p-type second semiconductor region formed on the first main surface side of the first substrate in a second area on the first main surface side of the first substrate;   a first insulating layer formed on the first semiconductor region in the first area;   a second insulating layer formed on the second semiconductor region in the second area;   a first semiconductor layer formed on the first insulating layer; and   a second semiconductor layer formed on the second insulating layer,   wherein the first MISFET and the fourth MISFET are formed on the first semiconductor layer,   the second MISFET, the third MISFET, the fifth MISFET and the sixth MISFET are formed on the second semiconductor layer,   the first substrate bias voltage is applied to the first semiconductor region, and   the second substrate bias voltage is applied to the second semiconductor region.   
     
     
         17 . The semiconductor integrated circuit device according to  claim 14 ,
 wherein the first channel type is an n-channel type,   the second channel type is a p-channel type,   the main circuit has a NOR circuit, and   the NOR circuit includes the first MISFET, the second MISFET, the third MISFET and an n-channel type eighth MISFET connected in parallel with the first MISFET.   
     
     
         18 . The semiconductor integrated circuit device according to  claim 17 , further comprising:
 a second substrate;   a p-type third semiconductor region formed on a second main surface side of the second substrate in a third area on the second main surface side of the second substrate;   an n-type fourth semiconductor region formed on the second main surface side of the second substrate in a fourth area on the second main surface side of the second substrate;   a third insulating layer formed on the third semiconductor region in the third area;   a fourth insulating layer formed on the fourth semiconductor region in the fourth area;   a third semiconductor layer formed on the third insulating layer; and   a fourth semiconductor layer formed on the fourth insulating layer,   wherein the first MISFET and the fourth MISFET are formed on the third semiconductor layer,   the second MISFET, the third MISFET, the fifth MISFET and the sixth MISFET are formed on the fourth semiconductor layer,   the first substrate bias voltage is applied to the third semiconductor region, and   the second substrate bias voltage is applied to the fourth semiconductor region &*   
     
     
         19 - 35 . (canceled)