Programmable resistance memory elements with electrode interface layer and memory devices including the same

Abstract

A memory element can include a first electrode comprising at least a first element; a second electrode formed of a conductive material; and a memory layer comprising a memory material programmable between different resistance states. The first element can be ion conductible within the memory material. A second electrode can include an interface layer in contact with the memory layer. The interface layer being formed by inclusion of at least one modifier element not present in a remainder of the second electrode and not ion conductible within the memory material.

What is claimed is: 
     
         1 . A memory element, comprising:
 a first electrode comprising at least a first element;   a second electrode formed of a conductive material; and   a memory layer disposed between the first electrode and a second electrode, the memory layer comprising a memory material programmable between different resistance states, the first element being ion conductible within the memory material; wherein   the second electrode includes an interface layer on a surface of the second electrode in contact with the memory layer, the interface layer formed by inclusion of at least one modifier element not present in a remainder of the second electrode, the modifier element not being ion conductible within the memory material.   
     
     
         2 . The memory element of  claim 1 , wherein:
 the modifier element is a non-metal.   
     
     
         3 . The memory element of  claim 2 , wherein:
 the modifier element is nitrogen.   
     
     
         4 . The memory element of  claim 2 , wherein:
 the modifier element is oxygen.   
     
     
         5 . The memory element of  claim 4 , wherein:
 the second electrode comprises a metal; and   the interface layer comprises an oxide of the metal.   
     
     
         6 . The memory element of  claim 2 , wherein:
 the modifier element is a semiconductor that is not included in the memory material.   
     
     
         7 . The memory element of  claim 1 , wherein:
 the interface layer has a thickness less than one half the thickness of the memory layer.   
     
     
         8 . A memory element, comprising:
 a first electrode comprising at least a first element;   a second electrode comprising at least second element;   a memory layer disposed between the first electrode and a second electrode, the memory layer comprising a memory material programmable between different resistance states, the first element being ion conductible within the memory material; and   an interface layer on a surface of the second electrode in contact with the memory layer, the interface layer formed by inclusion of at least one modifier element not present in a remainder of the second electrode, the modifier element being a non-metal.   
     
     
         9 . The memory element of  claim 8 , wherein:
 the modifier element is selected from the group of: oxygen and nitrogen.   
     
     
         10 . The memory element of  claim 9 , wherein:
 the interface layer comprises an oxide of the second element.   
     
     
         11 . The memory element of  claim 9 , wherein:
 the interface layer comprises a nitride of the second element.   
     
     
         12 . The memory element of  claim 8 , wherein:
 the modifier element is a semiconductor.   
     
     
         13 . The memory element of  claim 8 , wherein:
 the first electrode, second electrode and memory layer are vertically stacked, the first electrode being a top electrode and the second electrode being a bottom electrode.   
     
     
         14 . A method, comprising:
 forming a first electrode;   forming an interface layer that extends into the first electrode by inclusion of at least one modifier element not present in a remainder of the second electrode;   forming a memory layer in contact with the interface layer, the memory layer comprising a memory material programmable between different resistance states; and   forming a second electrode comprising a first element that is ion conductible within the memory material; wherein the modifier element is not ion conductible within the memory material.   
     
     
         15 . The method of  claim 14 , wherein:
 forming the interface layer includes treating an exposed surface of the first electrode.   
     
     
         16 . The method of  claim 15 , wherein:
 treating the exposed surface of the first electrode includes subjecting the surface to a temperature cycle.   
     
     
         17 . The method of  claim 15 , wherein:
 treating the exposed surface of the first electrode includes oxidizing the surface.   
     
     
         18 . The method of  claim 15 , wherein:
 treating the exposed surface of the first electrode includes implanting atoms of the modifier element into the surface.   
     
     
         19 . The method of  claim 15 , wherein:
 treating the exposed surface of the first electrode includes exposing the surface to a plasma that includes a gas comprising the modifier element.   
     
     
         20 . The method of  claim 14 , wherein:
 forming the interface layer includes adding the modifier element in situ as the first electrode is formed.