Display device, semiconductor device, and driving method thereof

Abstract

An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a first pixel;   a second pixel;   a third pixel; and   a shift register comprising:
 a first transistor; 
 a second transistor; 
 a third transistor; 
 a fourth transistor; 
 a fifth transistor; 
 a sixth transistor; 
 a seventh transistor; and 
 an eighth transistor, 
   wherein a ratio of a channel width to a channel length of the second transistor is higher than a ratio of a channel width to a channel length of the first transistor,   wherein the ratio of the channel width to the channel length of the second transistor is higher than a ratio of a channel width to a channel length of the third transistor,   wherein the ratio of the channel width to the channel length of the second transistor is higher than a ratio of a channel width to a channel length of the fourth transistor,   wherein a ratio of a channel width to a channel length of the sixth transistor is higher than a ratio of a channel width to a channel length of the fifth transistor,   wherein the ratio of the channel width to the channel length of the sixth transistor is higher than a ratio of a channel width to a channel length of the seventh transistor,   wherein the ratio of the channel width to the channel length of the sixth transistor is higher than a ratio of a channel width to a channel length of the eighth transistor,   wherein the first pixel is electrically connected to a first line,   wherein the second pixel is electrically connected to a second line,   wherein the third pixel is electrically connected to a third line,   wherein one of a source and a drain of the first transistor is electrically connected to the first line, the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,   wherein one of a source and a drain of the second transistor is electrically connected to a fourth line, the other of the source and the drain of the second transistor is electrically connected to the second line,   wherein one of a source and a drain of the third transistor is electrically connected to the second line,   wherein the other of the source and the drain of the third transistor is electrically connected to the gate of the second transistor,   wherein a gate of the third transistor is electrically connected to the fourth line,   wherein one of a source and a drain of the fourth transistor is electrically connected to the first line, the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to the second line,   wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the sixth transistor,   wherein one of a source and a drain of the sixth transistor is electrically connected to a fifth line,   wherein the other of the source and the drain of the sixth transistor is electrically connected to the third line,   wherein one of a source and a drain of the seventh transistor is electrically connected to the third line,   wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the sixth transistor,   wherein a gate of the seventh transistor is electrically connected to the fifth line,   wherein one of a source and a drain of the eighth transistor is electrically connected to the second line,   wherein the other of the source and the drain of the eighth transistor is electrically connected to the gate of the sixth transistor,   wherein the first line, the second line, the third line, the fourth line, and the fifth line are each a different line,   wherein the fourth line is capable of transmitting a first clock signal,   wherein the fifth line is capable of transmitting a second clock signal, and   wherein at least one of each channel region of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor includes an oxide semiconductor,   wherein each one of the first transistor, the second transistor, the third transistor and the fourth transistor comprises:   a first insulating layer over and at least partly in contact with the channel region; and   a second insulating layer over the first insulating layer,   wherein the first insulating layer includes silicon and oxygen,   wherein the second insulating layer includes silicon and nitrogen, and   wherein each off-state current of at least the first transistor is 1 aA/μm or less.   
     
     
         3 . A display device comprising the semiconductor device according to  claim 2 . 
     
     
         4 . An electronic appliance comprising the semiconductor device according to  claim 2 , the electronic appliance comprising at least one of a speaker, an image reception portion, a sensor, a microphone, an LED lamp, and an antenna. 
     
     
         5 . The semiconductor device according to  claim 2 , wherein the second insulating layer is at least partly in contact with the first insulating layer. 
     
     
         6 . The semiconductor device according to  claim 2 , wherein the first line is configured to supply a start pulse signal. 
     
     
         7 . A semiconductor device comprising:
 a first pixel;   a second pixel;   a third pixel; and   a shift register comprising:
 a first transistor; 
 a second transistor; 
 a third transistor; 
 a fourth transistor; 
 a fifth transistor; 
 a sixth transistor; 
 a seventh transistor; and 
 an eighth transistor, 
   wherein a ratio of a channel width to a channel length of the second transistor is higher than a ratio of a channel width to a channel length of the first transistor,   wherein the ratio of the channel width to the channel length of the second transistor is higher than a ratio of a channel width to a channel length of the third transistor,   wherein the ratio of the channel width to the channel length of the second transistor is higher than a ratio of a channel width to a channel length of the fourth transistor,   wherein a ratio of a channel width to a channel length of the sixth transistor is higher than a ratio of a channel width to a channel length of the fifth transistor,   wherein the ratio of the channel width to the channel length of the sixth transistor is higher than a ratio of a channel width to a channel length of the seventh transistor,   wherein the ratio of the channel width to the channel length of the sixth transistor is higher than a ratio of a channel width to a channel length of the eighth transistor,   wherein the first pixel is electrically connected to a first line,   wherein the second pixel is electrically connected to a second line,   wherein the third pixel is electrically connected to a third line,   wherein one of a source and a drain of the first transistor is electrically connected to the first line, the other of the source and the drain of the first transistor is electrically connected to a gate of the second transistor,   wherein one of a source and a drain of the second transistor is electrically connected to a fourth line, the other of the source and the drain of the second transistor is electrically connected to the second line,   wherein one of a source and a drain of the third transistor is electrically connected to the second line,   wherein the other of the source and the drain of the third transistor is electrically connected to the gate of the second transistor,   wherein a gate of the third transistor is electrically connected to the fourth line,   wherein one of a source and a drain of the fourth transistor is electrically connected to the first line, the other of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to the second line,   wherein the other of the source and the drain of the fifth transistor is electrically connected to a gate of the sixth transistor,   wherein one of a source and a drain of the sixth transistor is electrically connected to a fifth line,   wherein the other of the source and the drain of the sixth transistor is electrically connected to the third line,   wherein one of a source and a drain of the seventh transistor is electrically connected to the third line,   wherein the other of the source and the drain of the seventh transistor is electrically connected to the gate of the sixth transistor,   wherein a gate of the seventh transistor is electrically connected to the fifth line,   wherein one of a source and a drain of the eighth transistor is electrically connected to the second line,   wherein the other of the source and the drain of the eighth transistor is electrically connected to the gate of the sixth transistor,   wherein the first line, the second line, the third line, the fourth line, and the fifth line are each a different line,   wherein the fourth line is capable of transmitting a first clock signal,   wherein the fifth line is capable of transmitting a second clock signal, and   wherein at least one of each channel region of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor includes an oxide semiconductor.   
     
     
         8 . The semiconductor device according to  claim 7 , wherein each off-state current of at least the first transistor is 1 aA/μm or less. 
     
     
         9 . A display device comprising the semiconductor device according to  claim 7 . 
     
     
         10 . An electronic appliance comprising the semiconductor device according to  claim 7 , the electronic appliance comprising at least one of a speaker, an image reception portion, a sensor, a microphone, an LED lamp, and an antenna. 
     
     
         11 . The semiconductor device according to  claim 7 , wherein the first line is configured to supply a start pulse signal. 
     
     
         12 . The semiconductor device according to  claim 2 ,
 wherein the shift register comprises a ninth transistor and a tenth transistor,   wherein the ratio of the channel width to the channel length of the second transistor is higher than a ratio of a channel width to a channel length of the ninth transistor,   wherein the ratio of the channel width to the channel length of the sixth transistor is higher than a ratio of a channel width to a channel length of the tenth transistor,   wherein one of a source and a drain of the ninth transistor is electrically connected to a sixth line,   wherein the other of the source and the drain of the ninth transistor is electrically connected to the second line,   wherein one of a source and a drain of the tenth transistor is electrically connected to the sixth line, and   wherein the other of the source and the drain of the tenth transistor is electrically connected to the third line.   
     
     
         13 . The semiconductor device according to  claim 12 ,
 wherein the shift register comprises an eleventh transistor and a twelfth transistor,   wherein the ratio of the channel width to the channel length of the second transistor is higher than a ratio of a channel width to a channel length of the eleventh transistor,   wherein the ratio of the channel width to the channel length of the sixth transistor is higher than a ratio of a channel width to a channel length of the twelfth transistor,   wherein one of a source and a drain of the eleventh transistor is electrically connected to the sixth line,   wherein the other of the source and the drain of the eleventh transistor is electrically connected to the second line,   wherein one of a source and a drain of the twelfth transistor is electrically connected to the sixth line, and   wherein the other of the source and the drain of the twelfth transistor is electrically connected to the third line.   
     
     
         14 . The semiconductor device according to  claim 7 ,
 wherein the shift register comprises a ninth transistor and a tenth transistor,   wherein the ratio of the channel width to the channel length of the second transistor is higher than a ratio of a channel width to a channel length of the ninth transistor,   wherein the ratio of the channel width to the channel length of the sixth transistor is higher than a ratio of a channel width to a channel length of the tenth transistor,   wherein one of a source and a drain of the ninth transistor is electrically connected to a sixth line,   wherein the other of the source and the drain of the ninth transistor is electrically connected to the second line,   wherein one of a source and a drain of the tenth transistor is electrically connected to the sixth line, and   wherein the other of the source and the drain of the tenth transistor is electrically connected to the third line.   
     
     
         15 . The semiconductor device according to  claim 14 ,
 wherein the shift register comprises an eleventh transistor and a twelfth transistor,   wherein the ratio of the channel width to the channel length of the second transistor is higher than a ratio of a channel width to a channel length of the eleventh transistor,   wherein the ratio of the channel width to the channel length of the sixth transistor is higher than a ratio of a channel width to a channel length of the twelfth transistor,   wherein one of a source and a drain of the eleventh transistor is electrically connected to the sixth line,   wherein the other of the source and the drain of the eleventh transistor is electrically connected to the second line,   wherein one of a source and a drain of the twelfth transistor is electrically connected to the sixth line, and   wherein the other of the source and the drain of the twelfth transistor is electrically connected to the third line.   
     
     
         16 . The semiconductor device according to  claim 12 , wherein the sixth line is configured to supply power supply voltage. 
     
     
         17 . The semiconductor device according to  claim 13 , wherein the sixth line is configured to supply power supply voltage.