Memory cell support lattice

Abstract

Memory cell support lattices and methods of forming the same are described herein. As an example, a method of forming a memory cell support lattice includes forming a mask on a number of capacitor elements in an array, such that a space between vertically and horizontally adjacent capacitor elements is fully covered and a space between diagonally adjacent capacitor elements is partially covered and forming a support lattice in a support material by etching the support material to remove portions of the support material below the openings in the mask.

1 - 20 . (canceled) 
     
     
         21 . A memory array, comprising:
 a self-aligned support lattice that surrounds a number of capacitor elements in a memory cell array;   wherein the self-aligned support lattice includes a number of openings diagonally between the number of capacitor elements; and   wherein the self-aligned support lattice provides support to the number of capacitor elements to limit lateral movement of the number of capacitor elements.   
     
     
         22 . The memory array of  claim 21 , wherein the self-aligned support lattice comprises a nitride material. 
     
     
         23 . The memory array of  claim 21 , wherein the self-aligned support lattice comprises an oxide material. 
     
     
         24 . The memory array of  claim 21 , wherein the array of memory cells includes DRAM memory cells. 
     
     
         25 . The memory array of  claim 21 , wherein the self-aligned support lattice comprises openings exposing a portion of the capacitor elements below the self-aligned support lattice. 
     
     
         26 . The memory array of  claim 21 , wherein the capacitor elements comprise titanium nitride (TiN). 
     
     
         27 . A memory array, comprising:
 a number memory cells, wherein each of the number of memory cells includes an access device and a capacitor element and wherein each capacitor element is surrounded by a support lattice having self-aligned openings diagonally between diagonally adjacent capacitor elements.   
     
     
         28 . The memory array of  claim 27 , wherein a number of access lines are coupled to the access devices of the number of memory cells. 
     
     
         29 . The memory array of  claim 27 , wherein a number of data lines are coupled to the capacitor elements of the number of memory cells. 
     
     
         30 . The memory array of  claim 27 , wherein the support lattice is recessed below an upper surface of each capacitor element. 
     
     
         31 . The memory array of  claim 27 , wherein the support lattice comprises openings exposing a portion of the capacitor elements below the self-aligned support lattice. 
     
     
         32 . The memory array of  claim 27 , wherein the support lattice provides support to limit lateral movement of each capacitor element. 
     
     
         33 . The memory array of  claim 27 , wherein the support lattice provides spacing between adjacent capacitor elements to prevent capacitor elements from contacting each other. 
     
     
         34 . A memory array, comprising:
 a number memory cells, wherein each of the number of memory cells includes an access device and a capacitor element;   wherein each capacitor element is surrounded by a support lattice having self-aligned openings diagonally between diagonally adjacent capacitor elements;   wherein the support lattice is continuous laterally between laterally adjacent capacitor elements; and   wherein the support lattice provides spacing between adjacent capacitor elements to prevent capacitor elements from contacting each other.   
     
     
         35 . The memory array of  claim 34 , wherein the support lattice is recessed below an upper surface of each capacitor element. 
     
     
         36 . The memory array of  claim 34 , wherein the support lattice is located on between an upper surface of each capacitor element and a dielectric material that surrounds each capacitor element. 
     
     
         37 . The memory array of  claim 34 , wherein the support lattice comprises a nitride material. 
     
     
         38 . The memory array of  claim 34 , wherein the support lattice comprises an oxide material. 
     
     
         39 . The memory array of  claim 34 , wherein each capacitor element is surrounded by a dielectric material below the support lattice. 
     
     
         40 . The memory array of  claim 39 , wherein the dielectric material is formed below the support lattice through the openings in the support lattice.