Method for power estimation for virtual prototyping models for semiconductors

Abstract

The present invention may comprise an apparatus and method for calculating power consumption, including a unit for generating a clock-level analysis without synthesis of an algorithm description and calculating operating ratios of storage elements and arithmetic units. The invention may also comprise a method for estimating the power to be consumed by a SystemC model. By estimating this value, a user may gauge the amount of power a specific semiconductor design might consume, once manufactured into a chip.

I claim: 
     
         1 . A method for measuring power in a virtual prototype for a model semiconductor design, the method comprising:
 identifying, within a netlist representing an integrated circuit, one or more transistors coupled to a voltage supply for which to estimate power as applied to a virtual prototype representing the integrated circuit;   generating a respective measurement statement for each of the one or more transistors, wherein the respective measurement statement is usable by a circuit simulation tool to measure the power consumed within the virtual prototype of a design block during a simulation of the virtual prototype representing the integrated circuit, without synthesizing the model; and,   creating a measurement file and placing respective measurement statements within the measurement file, wherein the measurement file is usable by the circuit simulation tool for performing the simulation of the integrated circuit.   
     
     
         2 . The method of  claim 1 , further comprising:
 running a simulation of the virtual prototype representing the integrated circuit, and generating a corresponding output file;   extracting, from the corresponding output file, results from at least some of a set of respective measurement statements; and   generating a power report based on the extracted results.   
     
     
         3 . The method of  claim 2 , further comprising:
 performing again the method of  claim 1 .   
     
     
         4 . The method of  claim 2 , further comprising:
 generating a graphical representation of a power estimate for the integrated circuit based on the power report.   
     
     
         5 . The method of  claim 1 , further comprising:
 running the simulation of the virtual prototype representing the integrated circuit and generating a corresponding log file;   extracting, from the corresponding log file, information associated with the simulation of the integrated circuit; and determining whether the simulation is valid based on the extracted information.   
     
     
         6 . A power evaluation method comprising:
 for each respective module of a plurality of modules:   providing an Electronic System Level Circuit Description (ESLCD) containing a plurality of operations of modules for analysis;   reviewing the ESLCD and identifying those operations of modules of the ESLCD that are equivalent to a previously analyzed case, a case comprising an operation of a module, and those operations of modules of the ESLCD that have no equivalent previously analyzed case;   for each operation of module of the ESLCD that is equivalent to a previously analyzed case, retrieving a power macro-model of the previously analyzed case from memory and assigning that power macro-model to that operation of module in the ESLCD;   for each operation of module of the ESLCD that has no equivalent previously analyzed case, generating a power macro-model for each operation of module and assigning that generated power macro-model to that operation of module in the ESLCD;   using the plurality of power macro-models, sample input vectors and sample output vectors, evaluating the power consumption of each of the operation of modules in the ESLCD and summing the power consumption of each of the operation of modules to provide a system level power estimate;   wherein the cases are defined by a circuit description and a context of the input stimuli under which the circuit is exercised;   wherein the context of the input stimuli under which the circuit is exercised further comprises a testbench description, the testbench description partitioned into segments; and   producing a monitor file wherein the monitor file comprises the test bench description and a pair of print statements associated with each segment in the testbench description, in which the print statements cause the simulation time of execution of the print statement to be printed to a designated file along with an identifier of the segment.   
     
     
         7 . The method of  claim 6 , further comprising:
 inserting commands into an overlay/monitor file to indicate which modules will have a power macro-model generated from their simulated activity.   
     
     
         8 . The method of  claim 7 , wherein the modules identified as needing power macro-models are simulated and have power macro-models constructed from the simulation. 
     
     
         9 . The method of  claim 6 , further comprising:
 increasing a number of timing modes to a number greater than three.   
     
     
         10 . The method of  claim 6 , further comprising:
 parsing an object file to determine variables.   
     
     
         11 . The method of  claim 6 , further comprising:
 building a table of virtual gates; and   calculating estimated power from a technology library.