Linear to physical address translation with support for page attributes

Abstract

Embodiments of the invention are generally directed to systems, methods, and apparatuses for linear to physical address translation with support for page attributes. In some embodiments, a system receives an instruction to translate a memory pointer to a physical memory address for a memory location. The system may return the physical memory address and one or more page attributes. Other embodiments are described and claimed.

What is claimed is: 
     
         1 . A machine-implemented method comprising:
 receiving an instruction to translate a virtual memory pointer to a physical memory address for a memory location;   translating the virtual memory pointer to the physical memory address based on page table information; and   returning the physical memory address and one or more page attributes.   
     
     
         2 . The method of  claim 1 , wherein translating the virtual memory pointer to the physical memory address based on page table information comprises:
 reading a translation look-aside buffer (TLB) entry to obtain the physical memory address and the one or more page attributes.   
     
     
         3 . The method of  claim 1 , wherein translating the virtual memory pointer to the physical memory address based on page table information comprises:
 if the TLB does not contain the physical memory address, then reading at least one page table entry to obtain the physical memory address and the one or more page attributes.   
     
     
         4 . The method of  claim 1 , wherein the one or more attributes include at least one of:
 a present bit,   a read/write bit,   a user/supervisor bit,   an access bit,   a dirty bit,   a global flag,   an execute disable bit,   a page size indicator, and   a translation page fault.   
     
     
         5 . The method of  claim 1  wherein returning the physical memory address and the one or more page attributes comprises:
 storing the physical memory address and the one or more page attributes in a dedicated register; and 
 accessing the dedicated register using, at least in part, microcode. 
 
     
     
         6 . The method of  claim 1 , wherein returning the physical memory address and the one or more page attributes comprises:
 returning the physical memory address and the one or more page attributes via a read return bus.   
     
     
         7 . The method of  claim 1 , wherein receiving the instruction to translate the virtual memory pointer to a physical memory address for a memory location includes receiving the instruction from a virtual machine manager; and
 further wherein returning the physical memory address and the one or more page attributes includes returning a host physical memory address.   
     
     
         8 . The method of  claim 1 , wherein receiving the instruction to translate the virtual memory pointer to a physical memory address for a memory location includes receiving the instruction from a guest operating system; and
 further wherein returning the physical memory address and the one or more page attributes includes returning a guest physical memory address.   
     
     
         9 . The method of  claim 1 , wherein receiving the instruction to translate the virtual memory pointer to a physical memory address for a memory location comprises:
 receiving an asynchronous instruction to translate the virtual memory pointer to a physical memory address, the instruction including an operand to define a context for the instruction.   
     
     
         10 . The method of  claim 1 , wherein translating the virtual memory pointer to the physical memory address based on page table information comprises:
 determining whether a page corresponding to the virtual memory pointer is in memory without based on page table information.   
     
     
         11 . A system comprising:
 a memory device; and   a processor and logic executable thereon to
 receive an instruction to translate a virtual memory pointer to a physical memory address for a memory location; 
 translate the virtual memory pointer to the physical memory address based on page table information; and 
 return the physical memory address and one or more page attributes. 
   
     
     
         12 . The system of  claim 11 , wherein the logic to translate the virtual memory pointer to the physical memory address based on page table information comprises:
 logic to read a translation look-aside buffer (TLB) entry to obtain the physical memory address and the one or more page attributes.   
     
     
         13 . The system of  claim 11 , wherein the logic to translate the virtual memory pointer to the physical memory address based on page table information comprises:
 logic to read a page table entry to obtain the physical memory address and the one or more page attributes, if the TLB does not contain the physical memory address.   
     
     
         14 . The system of  claim 11 , wherein the one or more attributes include at least one of:
 a present bit,   a read/write bit,   a user/supervisor bit,   an access bit,   a dirty bit,   a global flag,   an execute disable bit,   a page size indicator, and   a translation page fault.   
     
     
         15 . The system of  claim 11 , wherein the logic to receive the instruction to translate the virtual memory pointer to a physical memory address for a memory location includes logic to receive the instruction from a virtual machine manager; and
 further wherein the logic to return the physical memory address and the one or more page attributes includes logic to return a host physical memory address.   
     
     
         16 . An article of manufacture comprising:
 an electronically accessible medium providing instructions that, when executed by an apparatus, cause the apparatus to
 receive an instruction to translate a virtual memory pointer to a physical memory address for a memory location; 
 translate the virtual memory pointer to the physical memory address based on page table information; and 
 return the physical memory address and one or more page attributes. 
   
     
     
         17 . The article of manufacture of  claim 16 , wherein the instructions that, when executed by the apparatus, cause the apparatus to translate the virtual memory pointer to the physical memory address based on page table information cause the apparatus to:
 read a translation look-aside buffer (TLB) entry to obtain the physical memory address and the one or more page attributes.   
     
     
         18 . The article of manufacture of  claim 16 , wherein the instructions that, when executed by the apparatus, cause the apparatus to translate the virtual memory pointer to the physical memory address based on page table information cause the apparatus to:
 read a page table entry to obtain the physical memory address and the one or more page attributes, if the TLB does not contain the physical memory address.   
     
     
         19 . The article of manufacture of  claim 16 , wherein the one or more attributes include at least one of:
 a present bit,   a read/write bit,   a user/supervisor bit,   an access bit,   a dirty bit,   a global flag,   an execute disable bit,   a page size indicator, and   a translation page fault.   
     
     
         20 . The article of manufacture of  claim 16 , wherein the instructions that, when executed by the apparatus, cause the apparatus to receive the instruction to translate the virtual memory pointer to a physical memory address for a memory location cause the apparatus to receive the instruction from a virtual machine manager;
 and further wherein the instructions that, when executed by the apparatus, cause the apparatus to return the physical memory address and the one or more page attributes cause the apparatus to return a host physical memory address.