Semiconductor memory device and method of controlling the same

Abstract

A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

1 . (canceled) 
     
     
         2 . A storage device comprising:
 a nonvolatile semiconductor memory configured to store a plurality of detecting codes to respectively detect an error in a plurality of data items, a plurality of first correcting codes to respectively correct an error in a plurality of first data blocks each of which comprises one of the data items and a corresponding detecting code, a second correcting code to correct an error in a second data block which comprises the first data blocks, and the second data block;   a first corrector configured to correct an error in the first data blocks using the first correcting codes, respectively;   a detector configured to detect an error in the data items corrected by the first corrector using the detecting codes, respectively; and   a second corrector configured to correct an error in a data item containing the error of the corrected data items using the second correcting code.   
     
     
         3 . The device according to  claim 2 , wherein an error correction capability of the second correcting code is higher than error correction capabilities of the first correcting codes. 
     
     
         4 . The device according to  claim 2 , wherein the second corrector stops a correction process when the data items corrected by the first corrector contain no error. 
     
     
         5 . The device according to  claim 2 , wherein the detector generates error information representing presence/absence of an error in each of the corrected data items. 
     
     
         6 . The device according to  claim 2 , wherein the semiconductor memory is a NAND flash memory. 
     
     
         7 . A storage device comprising:
 a nonvolatile semiconductor memory configured to store a plurality of detecting codes to respectively detect an error in a plurality of data items, a plurality of first correcting codes to respectively correct an error in a plurality of first data blocks each of which comprises one of the data items and a corresponding detecting code, a second correcting code to correct an error in a second data block which comprises the first data blocks, and the second data block;   a first corrector receiving the first data blocks and configured to correct an error in the first data blocks using the first correcting codes, respectively;   a detector receiving the data items corrected by the first corrector and configured to detect an error in the corrected data items using the detecting codes, respectively; and   a second corrector receiving the second data block corrected by the first corrector and configured to correct an error in the corrected second data block using the second correcting code, based on a detection result by the detector.   
     
     
         8 . The device according to  claim 7 , wherein an error correction capability of the second correcting code is higher than error correction capabilities of the first correcting codes. 
     
     
         9 . The device according to  claim 7 , wherein the second corrector stops a correction process when the data items corrected by the first corrector contain no error. 
     
     
         10 . The device according to  claim 7 , wherein the detector generates error information representing presence/absence of an error in each of the corrected data items. 
     
     
         11 . The device according to  claim 7 , wherein the semiconductor memory is a NAND flash memory. 
     
     
         12 . A storage device comprising:
 a nonvolatile semiconductor memory configured to store first data;   a first corrector configured to correct first error data in the first data using first correcting code data;   a detector configured to detect second error data which has not been corrected by the first corrector, using detecting code data; and   a second corrector configured to correct the second error data using second correcting code data.   
     
     
         13 . A storage device comprising:
 a nonvolatile semiconductor memory configured to store data; and   a processor for controlling the nonvolatile memory configured to correct data by using first error correcting codes, wherein   the processor monitors error bit levels at read operations to prevent data corruption caused by a number of accumulated error bits exceeding a correcting capability of the first error correcting codes, and   when the number of error bits reaches a threshold, the processor restores the data to its original, error-free state without using the first error correcting codes.   
     
     
         14 . The device according to  claim 13 , wherein the processor uses a BCH ECC algorithm per data unit which is an integral multiple of 512 bytes. 
     
     
         15 . The device according to  claim 13 , wherein the data is written into the nonvolatile semiconductor memory by page unit. 
     
     
         16 . The device according to  claim 15 , wherein
 the data is erased from the nonvolatile semiconductor memory by block unit, and   the block comprises pages.   
     
     
         17 . The device according to  claim 13 , wherein the processor uses a CRC (cyclic redundancy checksum) as an error detecting code. 
     
     
         18 . The device according to  claim 13 , further comprising:
 an interface;   a first circuit coupled to the interface;   a second circuit for interfacing with the memory; and   a third circuit coupled to the second circuit,   wherein the first circuit is configured to:   generate first error detection data for data received from the interface; and   check data transmitted to the interface,   wherein the third circuit is configured to check data and error correction data received from the second circuit.   
     
     
         19 . The device according to  claim 18 , wherein the first circuit is configured to generate error detection data per received unit of data. 
     
     
         20 . The device according to  claim 19 , wherein the data received from the interface comprises a data payload including a number of units of data, and
 the data received from the interface comprises streaming data.   
     
     
         21 . The device according to  claim 18 , wherein
 the first circuit comprises a cyclic redundancy check (CRC) engine coupled to the interface, and   the third circuit comprises an error correction code (ECC) engine.   
     
     
         22 . The device according to  claim 18 , wherein the processor includes:
 a fourth circuit coupled to the interface and to the second and third circuits; and   an error detection memory coupled to the fourth circuit,   wherein the error detection memory is configured to store the error detection data.   
     
     
         23 . The device according to  claim 22 , wherein the processor includes a data buffer coupled to the fourth circuit and to the third circuit,
 wherein the data buffer is configured to buffer data for the third circuit.   
     
     
         24 . The device according to  claim 18 , wherein the third circuit is configured to correct one or more errors in the data received from the second circuit. 
     
     
         25 . The device according to  claim 18 , wherein the processor is configured to transfer the data received from the interface, the error detection data, and the error correction data across the second circuit. 
     
     
         26 . The device according to  claim 18 , wherein the processor includes:
 a fourth circuit coupled to the interface and to the second and third circuits,   wherein the fourth circuit is configured to receive data and corresponding error detection data from the second circuit and to transfer the data and the corresponding error detection data to the first circuit.   
     
     
         27 . The device according to  claim 26 , wherein the first circuit is configured to:
 generate error detection data for the data received from the fourth circuit; and   compare the generated error detection data for the data received from the fourth circuit to corresponding error detection data received from the fourth circuit.   
     
     
         28 . The device according to  claim 26 , wherein the processor includes:
 more than one channel;   a channel data transfer circuit coupled to the fourth circuit;   a data buffer coupled to the channel data transfer circuit and the third circuit; and   an error detection circuit coupled to the second circuit.   
     
     
         29 . A storage device comprising:
 a nonvolatile semiconductor memory configured to store data; and   a processor for controlling the nonvolatile memory configured to correct data by using first error correcting codes, wherein   the processor refers to error bit levels at a read operation, and   when a number of error bits accumulated in the read transaction exceeds a correcting capability of the first error correcting codes, the processor processes the data to its original, error-free state using a method except for an algorithm using the first error correcting code.   
     
     
         30 . The device according to  claim 29 , wherein the processor uses a BCH ECC algorithm per data unit which is an integral multiple of 512 bytes. 
     
     
         31 . The device according to  claim 29 , wherein the data is written into the nonvolatile semiconductor memory by page unit. 
     
     
         32 . The device according to  claim 31 , wherein
 the data is erased from the nonvolatile semiconductor memory by block unit, and   the block comprises pages.   
     
     
         33 . The device according to  claim 29 , wherein the processor uses a CRC (cyclic redundancy checksum) as an error detecting code. 
     
     
         34 . The device according to  claim 29 , further comprising:
 an interface;   a first circuit coupled to the interface;   a second circuit for interfacing with the memory; and   a third circuit coupled to the second circuit,   wherein the first circuit is configured to:   generate first error detection data for data received from the interface; and   check data transmitted to the interface,   wherein the third circuit is configured to check data and error correction data received from the second circuit.   
     
     
         35 . The device according to  claim 34 , wherein the first circuit is configured to generate error detection data per received unit of data. 
     
     
         36 . The device according to  claim 35 , wherein the data received from the interface comprises a data payload including a number of units of data, and
 the data received from the interface comprises streaming data.   
     
     
         37 . The device according to  claim 34 , wherein
 the first circuit comprises a cyclic redundancy check (CRC) engine coupled to the interface, and   the third circuit comprises an error correction code (ECC) engine.   
     
     
         38 . The device according to  claim 34 , wherein the processor includes:
 a fourth circuit coupled to the interface and to the second and third circuits; and   an error detection memory coupled to the fourth circuit,   wherein the error detection memory is configured to store the error detection data.   
     
     
         39 . The device according to  claim 38 , wherein the processor includes a data buffer coupled to the fourth circuit and to the third circuit,
 wherein the data buffer is configured to buffer data for the third circuit.   
     
     
         40 . The device according to  claim 34 , wherein the third circuit is configured to correct one or more errors in the data received from the second circuit. 
     
     
         41 . The device according to  claim 34 , wherein the processor is configured to transfer the data received from the interface, the error detection data, and the error correction data across the second circuit. 
     
     
         42 . The device according to  claim 34 , wherein the processor includes:
 a fourth circuit coupled to the interface and to the second and third circuits,   wherein the fourth circuit is configured to receive data and corresponding error detection data from the second circuit and to transfer the data and the corresponding error detection data to the first circuit.   
     
     
         43 . The device according to  claim 42 , wherein the first circuit is configured to:
 generate error detection data for the data received from the fourth circuit; and   compare the generated error detection data for the data received from the fourth circuit to corresponding error detection data received from the fourth circuit.   
     
     
         44 . The device according to  claim 42 , wherein the processor includes:
 more than one channel;   a channel data transfer circuit coupled to the fourth circuit;   a data buffer coupled to the channel data transfer circuit and the third circuit; and   an error detection circuit coupled to the second circuit.