Processor with Messaging Network Technology

Abstract

An advanced processor comprises a plurality of multithreaded processor cores each having a data cache and instruction cache. A data switch interconnect is coupled to each of the processor cores and configured to pass information among the processor cores. A messaging network is coupled to each of the processor cores and a plurality of communication ports. In one aspect of an embodiment of the invention, the data switch interconnect is coupled to each of the processor cores by its respective data cache, and the messaging network is coupled to each of the processor cores by its respective message station. Advantages of the invention include the ability to provide high bandwidth communications between computer systems and memory in an efficient and cost-effective manner.

What is claimed is: 
     
         1 . A processor, comprising:
 a plurality of processor cores;   a cache;   a main memory;   a memory bridge; and   a data switch interconnect ring configured to pass data among the plurality of processor cores, the cache, and the memory bridge to enable access to the main memory.   
     
     
         2 . The processor of  claim 1 , further comprising:
 a messaging network ring;   an interface switch interconnect ring coupled to the messaging network ring; and   a plurality of communication ports coupled to the messaging network ring via the interface switch interconnect ring, the messaging network ring configured to transfer information between the plurality of processor cores and at least one of the plurality of communication ports,   wherein the data switch interconnect ring is directly coupled to each of the plurality of processor cores,   wherein the messaging network ring is directly coupled to each of the plurality of processor cores, and   wherein the data switch interconnect ring, the messaging network ring, and the interface switch interconnect ring are separate and distinct from each other.   
     
     
         3 . The processor of  claim 1 , further comprising:
 a plurality of data caches, each data cache of the plurality of data caches being associated with a respective processor core of the plurality of processor cores,   wherein the data switch interconnect ring is coupled to each of the plurality of processor cores by its respective data cache.   
     
     
         4 . The processor of  claim 2 , wherein the plurality of communication ports comprises:
 two or more of: an RGMII port, an XGMII port, and a PCI-X port.   
     
     
         5 . The processor of  claim 2 , further comprising:
 a plurality of instruction caches, each instruction cache of the plurality of instruction caches associated with a respective processor core of the plurality of processor cores,   wherein the messaging network ring is coupled to each of the plurality of processor cores by its respective instruction cache.   
     
     
         6 . The processor of  claim 2 , wherein the interface switch interconnect ring is configured to pass information between the messaging network ring and the plurality of communication ports. 
     
     
         7 . The processor of  claim 2 , wherein the messaging network ring is configured to transfer information between at least two of the plurality of processor cores and any of the plurality of communication ports. 
     
     
         8 . The processor of  claim 2 , wherein each of the plurality of processor cores is multithreaded, and wherein the interface switch interconnect ring is configured to pass the information between the messaging network ring and the plurality of communication ports. 
     
     
         9 . A processor, comprising:
 a plurality of processor cores, each of the plurality of processor cores comprising a first set of ports and a second set of ports, the first set of ports being different from the second set of ports;   a cache;   a memory bridge;   a main memory;   a data switch interconnect ring coupled to each of the plurality of processor cores through the first set of ports, the data switch interconnect ring being configured to pass data among the plurality of processor cores, the cache, and the memory bridge to enable access to the main memory; and   a messaging network ring coupled to each of the plurality of processor cores through the second set of ports.   
     
     
         10 . The processor of  claim 9 , further comprising:
 an interface switch interconnect ring coupled to the messaging network ring; and   a plurality of communication ports coupled to the messaging network ring via the interface switch interconnect ring, the messaging network ring being configured to transfer information between at least two of the plurality of processor cores and at least one of the plurality of communication ports,   wherein the data switch interconnect ring, the messaging network ring, and the interface switch interconnect ring are separate and distinct from each other   
     
     
         11 . The processor of  claim 10 , wherein the plurality of communication ports comprises:
 two or more of: an RGMII port, an XGMII port, and a PCI-X port.   
     
     
         12 . The processor of  claim 9 , further comprising:
 a plurality of data caches, each data cache of the plurality of data caches associated with a respective processor core of the plurality of processor cores,   wherein the data switch interconnect ring is coupled to each of the plurality of processor cores by its respective data cache.   
     
     
         13 . The processor of  claim 9 , further comprising:
 a plurality of instruction caches, each instruction cache of the plurality of instruction caches associated with a respective processor core of the plurality of processor cores,   wherein the messaging network ring is coupled to each of the plurality of processor cores by its respective instruction cache.   
     
     
         14 . The processor of  claim 10 , wherein the interface switch interconnect ring is configured to pass information between the messaging network ring and the plurality of communication ports. 
     
     
         15 . The processor of  claim 10 , wherein the messaging network ring is configured to transfer information between at least two of the plurality of processor cores and any of the plurality of communication ports. 
     
     
         16 . The processor of  claim 10 , wherein each of the plurality of processor cores is multithreaded, and wherein the interface switch interconnect ring is configured to pass the information between the messaging network ring and the plurality of communication ports. 
     
     
         17 . A processor, comprising:
 a plurality of processor cores;   a messaging network ring directly coupled to each of the plurality of processor cores;   a data switch interconnect ring directly coupled to each of the plurality of processor cores and configured to pass data between the plurality of processor cores; and   a plurality of communication ports coupled to the messaging network ring via the interface switch interconnect ring, the messaging network ring configured to transfer information between at least one of the plurality of communication ports.   
     
     
         18 . The processor of  claim 17 , further comprising:
 an interface switch interconnect ring coupled to the messaging network ring,   wherein the plurality of communication ports is coupled to the messaging network ring via the interface switch interconnect ring, and   wherein the data switch interconnect ring, the messaging network ring, and the interface switch interconnect ring are separate and distinct from each other.   
     
     
         19 . The processor of  claim 17 , further comprising:
 a plurality of data caches, each data cache of the plurality of data caches associated with a respective processor core of the plurality of processor cores,   wherein the data switch interconnect ring is coupled to each of the plurality of processor cores by its respective data cache.   
     
     
         20 . The processor of  claim 18 , wherein the interface switch interconnect ring is configured to pass the information between the messaging network ring and the plurality of communication ports.