Finfet with stressors

Abstract

A fin type transistor includes a dielectric layer on a substrate surface which serves to isolate the gate of the transistor from the substrate. The dielectric layer includes a non-selectively etched surface to produce top portions of fin structures which have reduced height variations across the wafer. The fin type transistor may also include a buried stressor and/or raised or embedded raised S/D stressors to cause a strain in the channel to improve carrier mobility.

What is claimed is:  
     
         1 . A device comprising:
 a substrate prepared with a dielectric layer on its top surface;   a fin structure disposed on the substrate in the dielectric layer, wherein the fin structure includes a bottom portion and a top portion, the top portion extending above a top surface of the dielectric layer;   a gate traversing the fin structure;   S/D regions in the fin structure adjacent to the gate;   a channel between the S/D regions below the gate; and   a first stressor to cause the channel to have a first strain to improve carrier mobility, wherein the fin structure comprises
 a first portion and a second portion above the first portion, and 
 a feature which reduces junction capacitance, wherein the feature is disposed partially beneath the gate and separating the first and second portions of the fin structure. 
   
     
     
         2 . The device of  claim 1  wherein the feature comprises a dielectric material. 
     
     
         3 . The device of  claim 2  wherein the dielectric material comprises a material which can be selectively removed with respect to the dielectric layer on the substrate. 
     
     
         4 . The device of  claim 2  wherein the first stressor is disposed in the first portion of the fin structure to cause the channel to have the first strain from below the channel. 
     
     
         5 . The device of  claim 2  wherein the first stressor comprises S/D stressors disposed on the S/D regions to cause the channel to have the first strain from above the channel. 
     
     
         6 . The device of  claim 2  wherein the first stressor comprises embedded raised S/D stressors disposed in recesses in the S/D regions to cause the channel to have the first strain from adjacent and above the channel. 
     
     
         7 . The device of  claim 1  wherein:
 the first portion of the fin structure comprises a lower part and an upper part; and 
 the feature is disposed in the upper part of the first portion of the fin structure and extends across a width of the fin structure, separating the lower part and the second portion of the fin structure. 
 
     
     
         8 . The device of  claim 1  wherein:
 the first portion of the fin structure comprises a lower part and an upper part; and 
 the feature is disposed in a part of the upper part of the first portion of the fin structure and does not extend across a width of the fin structure. 
 
     
     
         9 . The device of  claim 1  wherein:
 the feature is disposed in a part of the first portion of the fin structure and the feature does not cut across a complete width of the first portion of the fin structure. 
 
     
     
         10 . The device of  claim 1  wherein the first stressor comprises S/D stressors disposed on the S/D regions to cause the channel to have the first strain from above the channel. 
     
     
         11 . The device of  claim 1  wherein the first stressor comprises embedded raised S/D stressors disposed in recesses in the S/D regions to cause the channel to have the first strain from adjacent and above the channel. 
     
     
         12 . The device of  claim 1  wherein the feature is disposed in the first portion of the fin structure. 
     
     
         13 . The device of  claim 1  wherein:
 the gate comprises a gate electrode and a gate dielectric layer, wherein the gate dielectric layer is disposed below the gate electrode and on an exposed bottom surface of the second portion of the fin structure. 
 
     
     
         14 . The device of  claim 1  further comprising a counter doped well which is disposed below the fin structure. 
     
     
         15 . The device of  claim 1  further comprising a hard mask layer disposed over a top surface of the fin structure. 
     
     
         16 . A device comprising:
 a substrate prepared with a dielectric layer on its top surface;   a fin structure disposed on the substrate in the dielectric layer, wherein the fin structure includes a bottom portion and a top portion, the top portion extending above the dielectric top surface, wherein
 the top portion determines a device height and the top surface reduces height variations of fin structures across the wafer; 
   a gate traversing the fin structure;   S/D regions in the fin structure adjacent to the gate;   a channel between the S/D regions below the gate; and   a first stressor to cause the channel to have a first strain to improve carrier mobility, wherein the fin structure comprises
 a first portion and a second portion above the first portion, and 
 a feature which reduces junction capacitance, wherein the feature is disposed partially beneath the gate and separating the first and second portions of the fin structure. 
   
     
     
         17 . The device of  claim 16  wherein the feature comprises a dielectric material. 
     
     
         18 . The device of  claim 17  wherein the dielectric material comprises a material which can be selectively removed with respect to the dielectric layer on the substrate. 
     
     
         19 . The device of  claim 17  wherein the dielectric material comprises silicon oxide. 
     
     
         20 . A device comprising:
 a substrate prepared with a dielectric layer on its top surface;   a fin structure disposed on the substrate in the dielectric layer, wherein the fin structure includes a bottom portion and a top portion, the top portion extending above the dielectric top surface, wherein
 the top portion determines a device height and the top surface reduces height variations of fin structures across the wafer; 
   a gate traversing the fin structure;   S/D regions in the fin structure adjacent to the gate;   a channel between the S/D regions below the gate; and   a first stressor to cause the channel to have a first strain to improve carrier mobility, wherein the fin structure comprises
 a first portion and a second portion above the first portion, and 
 a dielectric feature partially beneath the gate and separating the first and second portions of the fin structure, wherein the dielectric feature reduces junction capacitance.