Field effect transistor (fet) with self-aligned contacts, integrated circuit (ic) chip and method of manufacture

Abstract

Field Effect Transistors (FETs), Integrated Circuit (IC) chips including the FETs, and a method of forming the FETs and IC. FET locations and adjacent source/drain regions are defined on a semiconductor wafer, e.g., a silicon on insulator (SOI) wafer. Source/drains are formed in source/drains regions. A stopping layer is formed on source/drains. Contact spacers are formed above gates. Source/drain contacts are formed to the stopping layer, e.g., after converting the stopping layer to silicide. The contact spacers separate source/drain contacts from each other.

What is claimed is: 
     
         1 . A method of forming Field Effect Transistors (FETs), said method comprising:
 defining FET locations on a semiconductor wafer;   forming gates in said FET locations source/drain regions being defined adjacent to said gates;   forming source/drains in said source/drain regions;   forming a stopping layer on said source/drains;   forming contact spacers above said gates; and   forming source/drain contacts to said stopping layer.   
     
     
         2 . A method of forming CMOS Integrated Circuit (IC) chips, said method comprising:
 defining Field Effect Transistor (FET) locations on a semiconductor wafer;   forming gates in defined said FET locations;   forming source/drains adjacent to said gates;   forming a stopping layer on said source/drains;   forming contact spacers above said gates;   converting said stopping layer to silicide;   forming source/drain contacts to the silicided source/drains; and   forming chip wiring connecting said FETs into chip circuits and connecting said chip circuits together.   
     
     
         3 . A Field Effect Transistor (FET) comprising:
 a semiconductor island in a surface of a semiconductor wafer;   a gate on a channel in said semiconductor island;   a dielectric cap encasing said gate on said semiconductor island;   a source/drain at said each end of said channel, each said source/drain having an upper surface above a lower surface of a respective said gate;   an insulating spacer above said gate on said dielectric cap; and   source/drain contacts self-aligned to said FET, said insulating spacer separating said self-aligned source/drain contacts.   
     
     
         4 . A FET as in  claim 3 , wherein said semiconductor wafer is a silicon on insulator (SOI) wafer, said surface is a surface silicon layer, said FET further comprising a silicide layer on each said raised source/drain. 
     
     
         5 . A FET as in  claim 4 , wherein said FET is a NFET and said each raised source/drain is phosphorous doped silicon (Si). 
     
     
         6 . A FET as in  claim 4 , wherein said FET is a PFET and said each raised source/drain is boron doped silicon germanium (SiGe). 
     
     
         7 . A FET as in  claim 4 , wherein said FET is one of a plurality of FETs on a CMOS Integrated Circuit (IC) chip, said plurality of FETs being connected together into chip circuits by chip wiring, said chip wiring connecting said chip circuits together. 
     
     
         8 . A CMOS Integrated Circuit (IC) chip comprising:
 a plurality of silicon islands in a surface silicon layer of a silicon on insulator (SOI) wafer, said plurality of silicon islands including a plurality of NFET islands and a plurality of PFET islands;   at least one gate on each NFET island and each PFET island;   a dielectric cap encasing each said at least one gate above a channel;   a raised source/drain at said each end of said channel, each said raised source/drain having an upper surface above an upper channel surface;   a silicide layer on each said raised source/drain;   self-aligned contacts to said source/drain regions;   an insulating spacer above said each at least one gate on said dielectric cap, said insulating spacer separating said self-aligned contacts; and   chip wiring connecting IC chip NFETs and PFETs into IC chip circuits and connecting said IC chip circuits together.   
     
     
         9 . A CMOS IC as in  claim 8 , wherein for each NFET each raised source/drain is phosphorous doped silicon (Si); and, for each PFET each raised source/drain is boron doped silicon germanium (SiGe).