Semiconductor device including passivation layer encapsulant

Abstract

A method of fabricating a semiconductor device includes forming a passivation layer on a least one capping layer of the semiconductor device, and forming an encapsulant layer on the passivation layer. The method further includes patterning the encapsulant layer to expose a portion of the passivation layer and forming a final via opening in the passivation layer. A conductive material is deposited in the final via opening. The method further includes planarizing the conductive material until reaching a remaining portion of the encapsulant layer such that the conductive material is flush with the encapsulant layer and the passivation layer is preserved.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a passivation layer formed on at least one capping layer of the semiconductor device;   an encapsulant layer formed on the passivation layer, the passivation layer including opposing buffer regions;   final via opening formed in the passivation layer and between the opposing buffer regions such that the buffer regions define the outer periphery of the final via opening; and   a conductive material deposited in the final via opening, the conductive material including an upper surface being flush with an upper surface of the encapsulant layer,   wherein the passivation layer has at least one preserved surface that is disposed against the encapsulant layer, the at least one preserved surface excluding at least one etched deformity.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the encapsulant layer is formed from a nitride material that is resistant to the chemical-mechanical planarization process. 
     
     
         3 . The semiconductor device of  claim 2 , further comprising a conductive liner formed on an upper surface and sidewalls of the passivation layer, and an upper surface of the at least one capping layer defined by the final via opening. 
     
     
         4 . The semiconductor device of  claim 3 , wherein the conductive material is an electroplating material formed on the conductive liner, the electroplating material filling the final via opening and covering the encapsulant layer. 
     
     
         5 . The semiconductor device of  claim 4 , wherein an upper surface of the encapsulant layer excludes the conductive liner and is flush with the electroplating material. 
     
     
         6 . The semiconductor device of  claim 5 , further comprising:
 a film cap that covers at least one contact pad disposed in a dielectric layer of the semiconductor device the at least one capping layer formed on the film cap; and   at least one terminal via opening formed in the at least one capping layer prior, the electroplating material filling the least one terminal via opening to form at least one electrically conductive terminal via that contacts the electroplating material and the at least one contact pad.   
     
     
         7 . The semiconductor device of  claim 6 , wherein the encapsulant layer has a thickness of no less than 1000 angstroms, and a patterned edge of the encapsulant layer extends completely to an edge of the final via opening. 
     
     
         8 . The semiconductor device of  claim 7 , wherein opposing walls of the final via opening have an angle being less than 90 degrees with respect to the at least one capping layer, the opposing walls being uniform with respect to one another. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the opposing buffer regions are interposed between a patterned edge of the encapsulant prior and the final via opening. 
     
     
         10 . The semiconductor device of  claim 5 , wherein an extended portion of the conductive liner is deposited on an upper surface of each buffer region. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the extended portion of the conductive liner is interposed between a respective buffer region and the conductive material so as to couple the conductive liner and the conductive material to the passivation layer. 
     
     
         12 . The semiconductor device of  claim 11 , wherein the conductive liner and the conductive material are each excluded from an upper surface of the at least one preserved surface.