Dynamic random access memory and boosted voltage producer therefor

Abstract

A dynamic random access memory (DRAM) is selectively operable in a sleep mode and another mode. The DRAM has data storage cells that are refreshed in the refresh mode. A boosted voltage is provided for the operation of the DRAM. A boosted voltage provider includes a group of charge pump circuits that are selectively activated by a pump control circuit based on a refresh time for refreshing data in the DRAM cells in the sleep mode.

1 . (canceled) 
     
     
         2 . A method comprising:
 providing an output voltage to be used for operation of a Dynamic Random Access Memory (DRAM);   determining whether the output voltage reaches a predetermined level to provide a determination result;   providing a plurality of enable signals in response to a refresh time when the DRAM is in a sleep mode, the refresh time being user-changeable; and   activating a number of a plurality of pump circuit segments of a charge pump in response to respective asserted enable signals of the plurality of enable signals, the charge pump for producing the output voltage, and the number of the plurality of pump circuit segments that are activated being inversely related to the refresh time.   
     
     
         3 . The method of  claim 2  further comprising:
 receiving a plurality of refresh time signals representing the refresh time; and 
 controlling the activating of the number of a plurality of pump circuit segments based on the plurality of refresh time signals. 
 
     
     
         4 . The method of  claim 2  further comprising performing a refresh operation using the output voltage. 
     
     
         5 . The method of  claim 2  wherein the providing of the output voltage includes pumping the output voltage in response to an oscillation signal provided in the sleep mode. 
     
     
         6 . The method of  claim 5  further comprising generating the oscillation signal in a sleep mode oscillator. 
     
     
         7 . The method of  claim 2  wherein at least one of the plurality of pump circuit segments receives a respective de-asserted enable signal of the plurality of enable signals and is thus not activated. 
     
     
         8 . The method of  claim 2  wherein the charge pump is a sleep mode pump circuit. 
     
     
         9 . The method of  claim 2  further comprising employing the output voltage to as at least one of a word bootstrapping voltage and a substrate bias voltage in the DRAM. 
     
     
         10 . The method of  claim 2  further comprising storing data in storage cells of the DRAM. 
     
     
         11 . The method of  claim 10  further comprising refreshing the data. 
     
     
         12 . The method of  claim 2  wherein each of the plurality of pump circuit segments provides substantially the same amount of charge. 
     
     
         13 . The method of  claim 2  further comprising providing a repetition signal to each of the plurality of pump circuit segments. 
     
     
         14 . The method of  claim 13  wherein each of the plurality of pump circuit segments includes a NAND gate that receives the repetition signal and a respective one of the plurality of enable signals. 
     
     
         15 . The method of  claim 2  wherein the refresh time is dynamically changeable based on operating conditions of the DRAM. 
     
     
         16 . The method of  claim 15  wherein at least one of the operating conditions is temperature. 
     
     
         17 . A method comprising:
 providing an output voltage to be used for operation of a memory device;   determining whether the output voltage reaches a predetermined level to provide a determination result;   providing a plurality of enable signals in response to a refresh time when the memory device is in a sleep mode, the refresh time being user-changeable; and   activating a number of a plurality of pump circuit segments of a charge pump in response to respective asserted enable signals of the plurality of enable signals, the charge pump for producing the output voltage, and the number of the plurality of pump circuit segments that are activated being inversely related to the refresh time.