Instruction and logic to provide simd secure hashing round slice functionality

Abstract

Instructions and logic provide SIMD secure hashing round slice functionality. Some embodiments include a processor comprising: a decode stage to decode an instruction for a SIMD secure hashing algorithm round slice, the instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings. Processor execution units, are responsive to the decoded instruction, to perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set, and store a result of the instruction in a SIMD destination register. One embodiment of the instruction specifies a hash round type as one of four MD5 round types. Other embodiments may specify a hash round type by an immediate operand as one of three SHA-1 round types or as a SHA-2 round type.

What is claimed is: 
     
         1 . A processor comprising:
 a plurality of SIMD registers;   a decode stage to decode a first instruction for a SIMD (Single Instruction Multiple Data) secure hashing algorithm round slice, the first instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings; and   one or more execution units, responsive to the decoded first instruction, to:
 perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set portion of rotate settings; and 
 store a result of the first instruction in a SIMD destination register. 
   
     
     
         2 . The processor of  claim 1 , wherein the first instruction specifies said SIMD destination register as a destination operand. 
     
     
         3 . The processor of  claim 1 , wherein for each round iteration of the secure hashing round-slice portion, said one or more execution units, responsive to the decoded first instruction:
 select a message-plus-constant for the round iteration from the message-plus-constant operand set,   process a portion of the source data operand set according to the round iteration, and   add the selected message-plus-constant to the processed portion of the source data operand set.   
     
     
         4 . The processor of  claim 1 , wherein the first instruction specifies said round-slice portion of the secure hashing algorithm round by a first field in an immediate operand. 
     
     
         5 . The processor of  claim 4 , wherein the first instruction specifies said rotator set portion of rotate settings by a second field in the immediate operand. 
     
     
         6 . The processor of  claim 4 , wherein said secure hashing algorithm comprises:
 an MD5 algorithm.   
     
     
         7 . The processor of  claim 4 , wherein said secure hashing algorithm comprises:
 a SHA-1 algorithm.   
     
     
         8 . The processor of  claim 4 , wherein said secure hashing algorithm comprises:
 a SHA-2 algorithm.   
     
     
         9 . A method comprising:
 storing in a first portion of a plurality of m data fields of a first vector register, an input state source operand of a hash algorithm;   storing in a second portion of the plurality of m data fields of a second vector register, a message-plus-constant operand set of the hash algorithm;   executing, in a processor, a SIMD (Single Instruction Multiple Data) instruction for a hash-round-slice having a plurality of iterations less than a total number of round iterations of the hash algorithm;   applying the message-plus-constant operand set and the rotator set portion of rotate settings in a secure hashing round-slice set of round iterations upon the source data operand set, and   for each iteration of the hash-round-slice, storing an output state generated as a result of the iteration, and bypassing the output state to the input state for each next iteration of the plurality of iterations.   
     
     
         10 . The method of  claim 9 , each iteration of the hash-round-slice comprising:
 selecting a message-plus-constant of an iteration from the message-plus-constant operand set,   processing a portion of the input state according to a round type specified by the SIMD instruction,   adding the selected message-plus-constant to the processed portion of the input state, and   generating a result of the iteration.   
     
     
         11 . The method of  claim 10 , wherein the first instruction specifies said hash round type as one of four MD5 round types. 
     
     
         12 . The method of  claim 11 , each iteration of the hash-round-slice further comprising:
 performing a bitwise rotate, according to a rotation value of a rotate set specified by the SIMD instruction, of the sum from adding the selected message-plus-constant to the processed portion of the input state.   
     
     
         13 . The method of  claim 9 , wherein the first instruction specifies said hash round type as one of three SHA-1 round types. 
     
     
         14 . The method of  claim 13 , each iteration of the hash-round-slice comprising:
 performing a bitwise rotate, according to a first rotation value of a rotate set specified by the SIMD instruction, of a first portion of the input state to generate a first rotated value;   performing a bitwise rotate, according to a second rotation value of a rotate set specified by the SIMD instruction, of a second portion of the input state to generate a second rotated value; and   adding the first rotated value to the sum from adding the selected message-plus-constant to the processed portion of the input state.   
     
     
         15 . The method of  claim 9 , wherein the first instruction specifies said hash round type as a SHA-2 round type. 
     
     
         16 . The method of  claim 9  wherein the SIMD instruction specifies said round type by a first field in an immediate operand. 
     
     
         17 . The method of  claim 16  wherein the SIMD instruction specifies a rotate set by a second field in the immediate operand. 
     
     
         18 . A processing system comprising:
 a memory to store a first instruction for a SIMD (Single Instruction Multiple Data) secure hashing algorithm round slice; and   a processor comprising:
 an instruction fetch stage to fetch the first instruction; 
 a decode stage to decode the first instruction, the first instruction specifying a source data operand set, a message-plus-constant operand set, a round-slice portion of the secure hashing algorithm round, and a rotator set portion of rotate settings; and 
 an execution stage, responsive to the decoded first instruction, to:
 perform a secure hashing round-slice set of round iterations upon the source data operand set, applying the message-plus-constant operand set and the rotator set portion of rotate settings; and 
 store a result of the first instruction in a SIMD destination register. 
 
   
     
     
         19 . The processing system of  claim 18 , wherein the first instruction specifies said round-slice portion of the secure hashing algorithm round by a field in an immediate operand. 
     
     
         20 . The processing system of  claim 18  wherein the first instruction specifies said rotator set portion of rotate settings by a field in the immediate operand.