Dynamic core switching

Abstract

A system including a first core to execute instructions associated with an application at a first speed based on a first instruction set and a second core to execute the instructions associated with the application at a second speed based on a second instruction set. The first speed is greater than the first speed. The second instruction set is a subset of the first instruction set. A first memory stores an operating system. The operating system includes a kernel that provides services to the application. A core switching module loads into a second memory after the operating system is booted, where the second memory is separate from the first memory, switches execution of the instructions associated with the application between the first core and the second core, and switches the execution of the instructions associated with the application between the first core and the second core transparently to the operating system.

What is claimed is: 
     
         1 . A system comprising:
 a first core to execute instructions associated with an application at a first speed based on a first instruction set;   a second core to execute the instructions associated with the application at a second speed based on a second instruction set, wherein the first speed is greater than the first speed, and wherein the second instruction set is a subset of the first instruction set;   a first memory to store an operating system, wherein the operating system includes a kernel that provides services to the application; and   a core switching module to   load into a second memory after the operating system is booted, wherein the second memory is separate from the first memory;   operate at a level above the kernel of the operating system; and   switch execution of the instructions associated with the application between the first core and the second core, transparently to the operating system and the application.   
     
     
         2 . The system of  claim 1 , wherein the first core and the second core execute the instructions associated with the application without translating the instructions in response to the core switching module switching the execution of the instructions between the first core and the second core. 
     
     
         3 . The system of  claim 1 , wherein the core switching module switches the execution of the instructions associated with the application between the first core and the second core based on one or more of processing load, type of the application, and resource utilization of the application. 
     
     
         4 . The system of  claim 1 , further comprising a glue logic module to activate only one of the first core and the second core at a time in response to the core switching module switching the execution of the instructions associated with the application between the first core and the second core. 
     
     
         5 . The system of  claim 1 , further comprising a core profile module to:
 generate an anticipated instruction execution rate for executing the instructions associated with the application based on at least one of a data cache miss rate, an instruction cache miss rate, and instructions per cycle executed by at least one of the first core and the second core;   wherein the core switching module is configured to switch the execution of the instructions associated with the application between the first core and the second core based on the anticipated instruction execution rate.   
     
     
         6 . The system of  claim 5 , further comprising:
 a core change sequence module to generate a core change sequence based on the anticipated instruction execution rate,   wherein the core switching module powers up one of the first core and the second core and shut down another of the first core and the second core based on the core change sequence.   
     
     
         7 . The system of  claim 1 , further comprising:
 a core activation module to stop processing of the application by the first core in response to disabling interrupts to the first core; and   a state transfer module to transfer a state of the first core to the second core in response to the stopping of the processing of the application by the first core.   
     
     
         8 . The system of  claim 7 , wherein the core activation module:
 allows the second core to resume execution of the instructions based on the state of the first core at the time of the stopping of the processing of the application by the first core; and   enables interrupts to the second core.   
     
     
         9 . The system of  claim 7 , wherein the core switching module supplies no power or standby power to the first core in response to the second core resuming execution of the instructions. 
     
     
         10 . A method comprising:
 storing an operating system in a first memory, wherein the operating system includes a kernel that provides services to an application;   loading a core switching module into a second memory after the operating system is booted, wherein the second memory is separate from the first memory;   operating the core switching module at a level above the kernel of the operating system; and   switching execution of instructions associated with the application between a first core and a second core transparently to the operating system and the application;   wherein the first core is configured to execute the instructions associated with the application at a first speed based on a first instruction set;   wherein the second core is configured to execute the instructions associated with the application at a second speed based on a second instruction set;   wherein the first speed is greater than the first speed; and   wherein the second instruction set is a subset of the first instruction set.   
     
     
         11 . The method of  claim 10 , further comprising executing the instructions associated with the application on the first core and the second core without translating the instructions in response to the switching of the execution of the instructions between the first core and the second core. 
     
     
         12 . The method of  claim 10 , further comprising switching the execution of the instructions associated with the application between the first core and the second core based on one or more of processing load, type of the application, and resource utilization of the application. 
     
     
         13 . The method of  claim 10 , further comprising activating only one of the first core and the second core at a time in response to switching the execution of the instructions associated with the application between the first core and the second core. 
     
     
         14 . The method of  claim 10 , further comprising:
 generating an anticipated instruction execution rate for executing the instructions associated with the application based on at least one of a data cache miss rate, an instruction cache miss rate, and instructions per cycle executed by at least one of the first core and the second core; and   switching the execution of the instructions associated with the application between the first core and the second core based on the anticipated instruction execution rate.   
     
     
         15 . The method of  claim 14 , further comprising:
 generating a core change sequence based on the anticipated instruction execution rate; and   powering up one of the first core and the second core and shutting down another of the first core and the second core based on the core change sequence.   
     
     
         16 . The method of  claim 10 , further comprising:
 stopping processing of the application by the first core in response to disabling interrupts to the first core; and   transferring a state of the first core to the second core in response to the stopping of the processing of the application by the first core.   
     
     
         17 . The method of  claim 16 , further comprising:
 allowing the second core to resume execution of the instructions based on the state of the first core at the time of the stopping of the processing of the application by the first core; and   enabling interrupts to the second core.   
     
     
         18 . The method of  claim 16 , further comprising supplying no power or standby power to the first core in response to the second core resuming execution of the instructions.